MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 844

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
Table 15-109
15.5.4
This section describes the ten-bit interface (TBI) and the TBI MII set of registers.
15.5.4.1
The eTSEC’s TBI implements the transmit portion of the physical coding sublayer as found in Clause 36
of IEEE 802.3z. In SerDes mode, packets conveyed across the GMII are encapsulated and encoded into
10-bit symbols and output to the SerDes. In GMII mode, the GMII signals are passed through to the
attached GMII PHY.
15.5.4.1.1
If TX_EN is de-asserted the eTSEC outputs an idle stream. If TX_EN is asserted, a Start_of_Packet
symbol is output. This symbol replaces the first byte of the preamble field. All other bytes of the packet
pass through an 8B10B encoding module. After the last byte of the FCS field is signaled via the GMII, the
MAC de-asserts TX_EN. The eTSEC then outputs an End_of_Packet symbol. Then, depending on the
position of the End_of_Packet symbols (being in either an odd or even position) the eTSEC outputs one
or two Carrier_Extend symbols. Following the last Carrier_Extend symbol, the eTSEC resumes sending
idle codes. If, during a packet, the eTSEC wishes to mark a byte invalid, TX_ER is asserted. The eTSEC,
upon detection of TX_ER, substitutes the data symbol for an Error_Propagation symbol.
15.5.4.1.2
Every eight-bit data octet has two (not necessarily different) ten-bit symbols associated with it. Depending
on the running disparity (the cumulative difference of ones and zeroes) the eTSEC module chooses the
appropriate symbol.
Special encapsulation symbols are called ordered_sets. Ordered_sets are comprised of one to four ten-bit
symbols. Ordered_sets can be found in Clause 36 of the IEEE 802.3z specification.
15.5.4.1.3
Because the idle ordered_set comprises two symbols and begins on an even symbols boundary, packets
can only begin on an even boundary. However, the GMII has no such restriction and may signal TX_EN
on an odd boundary. If this happens, the eTSEC delays the Start_of_Packet symbol, effectively ignoring
the first byte of preamble; thus, a seven octet preamble becomes six octets on the Ten-Bit Interface.
15-114
29–31
0–28 RFBPTR Pointer to the last free BD in RxBD Ring n . When RBASE n is updated, eTSEC initializes RFBPTR n
Bits
Name
Ten-Bit Interface (TBI)
—
TBI Transmit Process
describes the fields of the RFBPTRn registers.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Packet Encapsulation
8B10B Encoding
Preamble Shortening
to the value in the corresponding RBASE n .
Software may update this register at any time to inform the eTSEC the location of the last free BD
in the ring. Note that the 3 least-significant bits of this register are read only and zero.
Reserved.
Table 15-109. RFBPTR0–RFBPTR7 Field Descriptions
Description
Freescale Semiconductor