MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 554

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.4.6.9.1
Within the context register, for use in CBC mode, are two 64-bit context data registers that allow the host
to read/write the contents of the initialization vector (IV):
The IV must be written prior to the message data. If the IV registers are written during message processing,
or the CBC mode bit is not set, a context error is generated.
The IV registers may only be read after processing has completed, as indicated by the setting of interrupt
done (DONE) in the AESU status register as shown in
(AESUSR)”. If the IV registers are read prior to assertion of interrupt done, an early read error is generated.
The IV registers must be read when changing context and restored to resume processing an interrupted
message (CBC mode only).
12.4.6.9.2
In counter mode, a random 128-bit initial counter value is incremented modulo 2
processed. The running counter is encrypted and exclusive-ORed with the plaintext to derive the
ciphertext, or with the ciphertext to recover the plaintext. The modulus exponent M can be set between 8
and 128 in multiples of 8. The value of M is specified by writing to context register 3 as described in
Figure
12.4.6.9.3
As was noted in the AESU mode register, SRT is not a new AES mode; it is an AESU method of
performing AES-CTR mode with reduced context loading overhead specifically for performing SRTP. It
should be used with descriptor type 0010_0 srtp. As with counter mode, a random 128-bit initial counter
value is incremented modulo 2
exclusive-ORed with the plaintext to derive the ciphertext, or with the ciphertext to recover the plaintext.
The modulus exponent M can be set between 8 and 128 in multiples of 8. The value of M is specified by
writing to context register 3 as described in
The only difference between SRT mode and CTR mode is that in SRT mode, the AES context is loaded
and read via context registers 1–3, with no requirement to access context registers 4–7. In CTR mode,
context registers 1–4 must be loaded with zeros, with the counter and modulus being loaded into and read
from context registers 5–7.
12-76
•
•
12-56.
IV1 holds the least significant bytes of the initialization vector (bytes 1–8).
IV2 holds the most significant bytes of the initialization vector (bytes 9–16).
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Context for CBC Mode
Context for Counter Mode
Context for SRT Mode
M
with each block processed. The running counter is encrypted and
Figure
12-56.
Section 12.4.6.5, “AESU Status Register
M
with each block
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