MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 480

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.1
The position of the SEC 2.1 (henceforth referred to as SEC) in the MPC8533E architecture is shown in
Figure
movement bottleneck normally associated with slave-only cores. The host processor accesses the SEC
through its device drivers using DDR system memory for data storage. The SEC resides in the peripheral
memory map of the processor; therefore, when an application requires cryptographic functions, it simply
creates descriptors for the SEC which define the cryptographic function to be performed and the location
of the data. The SEC’s bus-mastering capability permits the host processor to set up a channel with a few
short register writes, leaving the SEC to perform reads and writes on system memory to complete the
required task.
12-2
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12-1. The SEC can act as a master on the internal system bus, allowing it to off-load the data
AFEU—ARC Four execution unit
— Implements a stream cipher compatible with the RC4 algorithm
— 40- to 128-bit programmable key
KEU—Kasumi execution unit
— Implements the Kasumi cipher
— Performs F8 encryption and F9 integrity checking as required for 3GPP
— Additionally performs A5/3 and GEA-3 modes as used in GSM, EDGE, and GPRS
MDEU—Message digest execution unit
— SHA with 160-bit, 224-bit, or 256-bit message digest
— MD5 with 128-bit message digest
— HMAC with either algorithm
RNG—Random number generator
XOR parity generation accelerator for RAID applications
Four crypto-channels, each supporting a queue of commands (descriptor pointers)
— Dynamic assignment of crypto-execution units via an integrated controller
— 256-byte buffer FIFOs on data input and output paths of each execution unit, with flow control
Master/slave logic, with DMA capability
— 36-bit address/64-bit data
— Master interface allows multiple pipelined requests
— DMA blocks can be on any byte boundary
Scatter/gather capability
— Gather capability enables the SEC 2.1 to concatenate multiple segments of memory when
— Similarly, scatter capability enables SEC 2.1 to write to multiple segments of memory when
SEC 2.1 Architecture Overview
for large data sizes
reading input data
writing output data
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor