MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 949

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 16-6
16.3.1.3
Current link descriptor address registers contain the address of the current link descriptor. In basic chaining
mode, shown in
memory.
Freescale Semiconductor
0–23
Bits
24
25
26
27
28
29
30
31
EOLNI End-of-links interrupt. After transferring the last block of data in the last link descriptor, if MR n [EOLSIE] is set,
EOLSI End-of-list interrupt. After transferring the last block of data in the last list descriptor, if MR n [EOLSIE] is set,
Name
EOSI End-of-segment interrupt. In chaining mode, after finishing a data transfer, if MR n [EOSIE] is set or if
CH
CB
TE
PE
—
—
describes the bits of the SRn.
ECLNDAR n )
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Current Link Descriptor Address Registers (CLNDAR n and
Reserved
Transfer error (Bit reset, write 1 to clear)
0 No error condition during the DMA transfer
1 Error condition during the DMA transfer. See
Reserved
Channel halted. Cleared automatically by hardware if MR n [CS] is set again for resuming a halted transfer
0 Channel is not halted. If software attempts to halt an idle channel (SR n [CB] is cleared), this bit will remain 0.
1 DMA transfer was successfully halted by software and can be resumed.
Programming error (bit reset, write 1 to clear)
0 No programming error detected
1 A programming error is detected that prevents the DMA transfer from occurring.
then this bit is set and an interrupt is generated.
(Bit reset, write 1 to clear)
Channel busy
0 DMA transfer is finished, an error occurred, or a channel abort occurred.
1 A DMA transfer is currently in progress.
CLNDAR n [EOSIE] is set, this bit gets set and an interrupt is generated. In direct mode, if MRn[EOSIE] is set,
this bit gets set and an interrupt is generated.
(Bit reset, write 1 to clear)
then this bit is set and an interrupt is generated.
(Bit reset, write 1 to clear)
Figure
16-6, software must initialize these registers to point to the first link descriptors in
Table 16-6. SR n Field Descriptions
Description
Section 16.4.3, “DMA Errors,”
for additional information.
DMA Controller
16-13