MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 586

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
from the slave interface and sends it to whichever internal location is indicated by the address. For a read,
the controller goes to the internal location and fetches the requested data from the specified address. The
SEC internal memory space must be accessed on modulo-4 boundaries to avoid invalid data or
unpredictable operation.
12.6.3
All SEC transactions are snooped by the e500 coherency module (ECM). This is part of the wiring of the
SEC interface and requires no user intervention.
12.6.4
All interrupt outputs from the channels, EUs, and bus interface are fed to the controller as interrupt
conditions. In addition, the controller itself detects some interrupt conditions. The controller maintains an
interrupt status register (ISR) with bits corresponding to all of these possible interrupt conditions. If an
interrupt condition occurs and the corresponding bit of the interrupt mask register (IMR) is high, then the
associated interrupt status register bit is set, indicating the presence of a pending interrupt. Whenever any
bits are set in the interrupt status register, the controller asserts its internal interrupt signal to the host.
To handle an interrupt, the host must read the interrupt status register (ISR) to determine the source. It may
then need to do further reads of interrupt status registers of other blocks to get more detailed information
about the cause. In some cases, the host may need to take action to clear the root cause of the interrupt.
After that, the host can clear the desired bit of the interrupt status register by writing a 1 to the
corresponding bit of the interrupt clear register (ICR) (and then write zeros to the end of interrupt register
in the PIC to enable additional SEC interrupts). If the cause of the interrupt condition has not been cleared,
or if there is some other interrupt condition from the same source, then the interrupt status register bit will
clear for a cycle and go high again, and the interrupt output line to the host remains high. If the interrupt
status register bit is successfully cleared and no other interrupt conditions are present, the controller
negates its interrupt output. If any interrupts are still pending in the interrupt status register, the interrupt
output remains asserted.
Note that EU interrupt conditions may be blocked at two different levels. There is an interrupt control
register in each EU which can block particular interrupt conditions before they reach the EU’s interrupt
status register, and in addition, bits of the controller’s interrupt mask register must be set to allow interrupt
conditions to reach the interrupt status register. Interrupt conditions from the channels and controller can
only be blocked through the interrupt mask register.
For typical operation it is suggested that the interrupt mask register be programmed as follows:
Errors or done signals coming from the EUs eventually cause the channel to signal an error or done
interrupt.
A channel can generate frequent interrupts, especially if it is configured to interrupt at the completion of
each descriptor. To make sure that the host receives the right number of interrupts, each channel done
interrupt has a special queuing feature. If multiple channel done interrupts are generated before the first is
cleared, then the additional interrupts are queued by the controller. When the host clears a channel
12-108
•
Leave channel interrupts enabled, while masking interrupts from the EUs.
Snooping by Caches
Controller Interrupts
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor