MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1093

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 18-37
Freescale Semiconductor
Offset 0x04
Reset
15–11
Bits
5–3
10
9
8
7
6
2
W
R
15
Bus master
Parity error
response
Interrupt
Disable
Name
SERR
—
—
—
—
describes the bits of the command register.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
Reserved
Controls the ability to generate INTx interrupt messages.
0 Enables INTx interrupt messages
1 Disables INTx interrupt messages
Any INTx emulation interrupts already asserted by this device must be deasserted when this bit is set.
Reserved
Controls the reporting of fatal and non-fatal errors detected by the device to the root complex.
0 Disables reporting
1 Enables reporting
Note: The error control and status bits in the command and status registers control PCI-compatible error
Reserved
Controls whether this PCI Express controller responds to parity errors.
0 Parity errors are ignored and normal operation continues.
1 Parity errors cause the appropriate bit in the PCI Express status register to be set. However, note that
Note: The error control and status bits in the command and status registers control PCI-compatible error
Reserved
Indicates whether this PCI Express device is configured as a master.
0 Disables the ability to generate PCI Express accesses
1 Enables this PCI Express controller to behave as a PCI Express bus master
EP mode: Clearing this bit prevent the device from issuing any memory or I/O transactions. Because MSI
interrupts are effectively memory writes, clearing this bit also disables the ability of the device to issue
MSI interrupts.
RC mode: Clearing this bit disables the ability of the device to forward memory transactions upstream.
This causes any inbound memory transaction to be treated as an unsupported request.
Table 18-37. PCI Express Command Register Field Descriptions
11
errors are reported based on the values set in the PCI Express error enable and detection registers.
reporting. PCI Express advanced error reporting is controlled by the PCI Express device control
register described in
advance error reporting capability structure described in sections 18.3.10.1 through 18.3.10.12.
reporting. PCI Express advanced error reporting is controlled by the PCI Express device control
register described in
advance error reporting capability structure described in sections 18.3.10.1 through 18.3.10.12.
Interrupt
Disable
10
Figure 18-39. PCI Express Command Register
—
9
SERR
Section 18.3.9.8, “PCI Express Device Control
Section 18.3.9.8, “PCI Express Device Control
8
— Parity error
7
All zeros
response
Description
6
5
—
3
Bus master
PCI Express Interface Controller
2
Register—0x54,” and the
Register—0x54,” and the
Memory
space
1
Access: Mixed
I/O space
0
18-45