MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 565

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.4.7.8
Following a done interrupt, the read-only KEU data out register holds the F9 message authentication code.
A 64-bit value is returned. This value may be truncated to 32 bits for some applications. Writing to this
location results in an address error being reflected in the KEU interrupt status register.
12.4.7.9
The KEU EU go register, shown in
has been written to the input FIFO. Writing to this register causes the KEU to process the final block of a
message, allowing it to signal DONE. When processing the last block, the value in the data size register
determines how many bits of the final message word (1–64) are processed. The value written to this
register does not matter. A read of this register always returns a zero value.
Freescale Semiconductor
Address KEU 0x3_E048
Bits
Reset
59
60
61
62
63
W
R
0
Name
OFU
IFO
IFE
—
—
KEU Data Out Register (F9 MAC) (KEUDOR)
KEU EU Go Register (KEUEUG)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
According to the ETSI/SAGE 3GPP specification for F9 (version 1.2), only
32 bits of the final MAC are used. This corresponds to the lower 4 bytes of
the KEU data out register.
Table 12-48. KEU Interrupt Control Register Field Descriptions (continued)
Input FIFO error. The KEU input FIFO was detected non-empty upon generation of done interrupt
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
Reserved
Input FIFO overflow. The KEU input FIFO was pushed while full.
0 Input FIFO overflow error enabled
1 Input FIFO overflow error disabled
Output FIFO underflow. The KEU output FIFO was read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
Reserved
Figure 12-64. KEU Data Out Register (F9 MAC)
Figure
12-65, is used to signal to the KEU that the final message block
KEU Data Out Register (F9 MAC)
NOTE
All zeros
Description
Security Engine (SEC) 2.1
Access: Read Only
12-87
63