MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 489

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 12-3
In this table and in the register figures and field descriptions, the following access definitions apply:
Freescale Semiconductor
Address Offset
0x3_C000–0x3_CFFF
0x3_A000–0x3_AFFF
0x3_E000–0x3_EFFF
0x3_2000–0x3_2FFF
0x3_4000–0x3_4FFF
0x3_6000–0x3_6FFF
0x3_8000–0x3_8FFF
•
•
•
•
•
(AD 17–0)
0x3_1BF8
0x3_1008
0x3_1010
0x3_1018
0x3_1020
0x3_1028
0x3_1030
0x3_1108
0x3_1110
0x3_1140
Address Offset
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
(AD 17–0)
shows the system address map showing all functional registers.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
IMR—Interrupt mask register
ISR—Interrupt status register
ICR—Interrupt clear register
ID—Identification register
IP block revision
EUASR—EU assignment status register
MCR—Master control register
CCCR1—Crypto-channel 1 configuration
register
CCPSR1—Crypto-channel 1 pointer
status register
CDPR1—Crypto-channel 1 current
descriptor pointer register
Module
MDEU
AESU
AFEU
PKEU
DEU
RNG
KEU
Table 12-2. SEC Base Address Map (continued)
Register
DES/3DES execution unit
AES execution unit
Message digest execution unit
Arc Four execution unit
Random number generator
Public key execution unit
Kasumi execution unit
Table 12-3. SEC Address Map
Controller
Channel 1
Description
Access
R/W
R/W
R/W
W
R
R
R
R
R
R
0xF0F0_F0F0_00FF_F0F0
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0030_0000_0010_0000
0x0030_0000_0010_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0007
0x0000_0000_0000_0000
0000_0000_0000_0000
Reset
Crypto EU
Type
Security Engine (SEC) 2.1
12.6.5.2/12-110
12.6.5.3/12-111
12.6.5.4/12-112
12.6.5.5/12-113
12.6.5.6/12-113
12.6.5.1/12-109
12.6.5.7/12-114
12.5.1.3/12-100
12.5.1.1/12-92
12.5.1.2/12-95
12.4.2/12-33
12.4.6/12-67
12.4.4/12-50
12.4.3/12-41
12.4.5/12-62
12.4.1/12-26
12.4.7/12-79
Reference
Reference
12-11