MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 531

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.4.4.2
The most common task likely to be executed via the MDEU is HMAC generation. HMACs are used to
provide message integrity within a number of security protocols, including IPSec, and TLS. The SSL 3.0
protocol uses a slightly different SSL-MAC. If an HMAC or SSL-MAC is to be performed using a single
descriptor (with the MDEU acting as sole or secondary EU), the following mode register bit settings
should be used:
To generate an HMAC for a message that is spread across a sequence of descriptors, the following mode
register bit settings should be used:
Freescale Semiconductor
62–63
Bits
57
58
59
60
61
SMAC Specifies whether to perform an SSL-MAC operation:
HMAC Specifies whether to perform an HMAC operation:
Name
EALG
CICV
INIT
ALG
Table 12-28. Mode Register —HMAC or SSL-MAC Generated by Single Descriptor
Recommended Settings for MDEU Mode Register
Table 12-27. MDEU Mode Register in New Configuration (NEW = 1) (continued)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Compare integrity check values.
0 Normal operation; no ICV comparison.
1 After the message digest (ICV) is computed, compare it to the data in the MDEU’s input FIFO. If the ICVs
0 Normal operation
1 Perform an SSL3.0 MAC operation. This requires a key and key length. If this is set then the HMAC bit
Initialization bit. Most operations will require this bit to be set. Cleared only for operations that load context from
a known intermediate hash value.
0 Do not initialize digest registers. In this case the registers must be loaded from a hash context pointer in the
1 Perform an algorithm-specific initialization of the digest registers.
0 Normal operation
1 Perform an HMAC operation. This requires a key and key length. If this is set then the SMAC bit should be 0.
The EALG (extended algorithm bit) and ALG (algorithm) bits together specify the message digest algorithm,
000 SHA-160 algorithm (full name for SHA-1)
001 SHA-256 algorithm
010 MD5 algorithm
011 SHA-224 algorithm
do not match, send an error interrupt to the channel. The number of bytes to be compared is given by the
ICV size register.
should be 0.
descriptor. When the data to be hashed is spread across multiple descriptors, this bit is set on all but the
first descriptor.
as follows:
Bits
56
58
59
60
SMAC
HMAC
CONT
Field
INIT
for HMAC
Description
0 (off)
0(on)
1(on)
1(on)
Value
SSL-MAC
0 (off)
1(on)
1(on)
0(on)
for
Security Engine (SEC) 2.1
12-53