MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 638

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
14.3.1.5
The refresh timer prescaler register (MRTPR), shown in
provide the SDRAM and UPM refresh timers clock.
Table 14-11
14.3.1.6
The memory data register (MDR), shown in
array for UPM read or write commands. MDR must be set up before issuing a write command to the UPM.
Table 14-12
14-20
8–31
0–31
Offset 0x084
Reset
Bits
Bits
0–7
W
R
Offset 0x088
Reset
0
Name
Name
PTP
—
D
W
R
describes MRTPR fields.
describes MDR[D].
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
Refresh timers prescaler. Determines the period of the refresh timers input clock. The system clock is divided
by PTP except when the value is 0000_0000, which represents the maximum divider of 256.
Reserved
The data to be read or written into the RAM array when a write or read command is supplied to the UPM
(M x MR[OP] = 01 or M x MR[OP] = 10).
Memory Refresh Timer Prescaler Register (MRTPR)
UPM Data Register (MDR)
PTP
Figure 14-8. Memory Refresh Timer Prescaler Register (MRTPR)
7
8
Table 14-11. MRTPR Field Descriptions
Figure 14-9. UPM Data Register (MDR)
Table 14-12. MDR Field Descriptions
Figure
14-9, contains data written to or read from the RAM
All zeros
All zeros
Description
Description
Figure
D
14-8, is used to divide the system clock to
—
Access: Read/Write
Freescale Semiconductor
Access: Read/Write
31
31