MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 617

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

and set the FIFO receiver trigger level UFCR[RTL] to control the received data available interrupt
UIER[ERDAI].
The UFCR also selects the type of DMA signaling. The UDSR[RXRDY] indicates the status of the
receiver FIFO. The DMA status registers (UDSR[TXRDY]) indicate when the transmitter FIFO is full.
When in FIFO mode, data written to UTHR is placed into the transmitter FIFO. The first byte written to
UTHR is the first byte onto the UART bus.
13.4.5.1
In FIFO mode, the UIER[ERDAI] is set when a time-out interrupt occurs. When a receive data time-out
occurs there is a maskable interrupt condition (through UIER[ERDAI]). See
Enable Register (UIER) (ULCR[DLAB] = 0),”
The interrupt ID register (UIIR) indicates if the FIFOs are enabled. Interrupt ID3 UIIR[IID3] bit is only
set for FIFO mode interrupts. The character time-out interrupt occurs when no characters have been
removed from or input to the receiver FIFO during the last four character times and there is at least one
character in the receiver FIFO during this time. The character time-out interrupt (controlled by UIIR[IID])
is cleared when the URBR is read. See
(ULCR[DLAB] = 0),”
The UIIR[FE] bits indicate if FIFO mode is enabled.
13.4.5.2
The UDSR[RXRDY] bit reflects the status of the receiver FIFO or URBR. In mode 0 (UFCR[DMS] is
cleared), UDSR[RXRDY] is cleared when there is at least one character in the receiver FIFO or URBR
and it is set when there are no more characters in the receiver FIFO or URBR. This occurs regardless of
the setting of the UFCR[FEN] bit. In mode 1 (UFCR[DMS] and UFCR[FEN] are set), UDSR[RXRDY]
is cleared when the trigger level or a time-out has been reached and it is set when there are no more
characters in the receiver FIFO.
The UDSR[TXRDY] bit reflects the status of the transmitter FIFO or UTHR. In mode 0 (UFCR[DMS] is
cleared), UDSR[TXRDY] is cleared when there are no characters in the transmitter FIFO or UTHR and it
is set after the first character is loaded into the transmitter FIFO or UTHR. This occurs regardless of the
setting of the UFCR[FEN] bit. In mode 1 (UFCR[DMS] and UFCR[FEN] are set), UDSR[TXRDY] is
cleared when there are no characters in the transmitter FIFO or UTHR and it is set when the transmitter
FIFO is full.
See
USDR[RXRDY] and USDR[TXRDY] bits.
13.4.5.3
An interrupt is active when DUART interrupt ID register bit 0 (UIIR[0]), is cleared. The interrupt enable
register (UIER) is used to mask specific interrupt types. For more details refer to the description of UIER
in
Freescale Semiconductor
Section 13.3.1.4, “Interrupt Enable Register (UIER) (ULCR[DLAB] = 0).”
Section 13.3.1.13, “DMA Status Registers (UDSR0, UDSR1),”
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
FIFO Interrupts
DMA Mode Select
Interrupt Control Logic
for more information.
Section 13.3.1.5, “Interrupt ID Registers (UIIR0, UIIR1)
for more details on interrupt enables.
for a complete description of the
Section 13.3.1.4, “Interrupt
DUART
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