MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 526

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.4.3.8
The interrupt control register, shown in
error (as defined in
bit in this register is set, the error is disabled; no error interrupt occurs and the interrupt status register is
not updated to reflect the error. If the corresponding bit is not set, then upon detection of an error, the
interrupt status register is updated to reflect the error, causing assertion of the error interrupt signal, and
causing the module to halt processing.
Table 12-25
12-48
Address AFEU 0x3_8038
0–50
Reset
Bits
51
52
53
54
55
56
57
58
W
R
0
Name
ERE
KSE
DSE
OFE
ME
CE
AE
—
IE
describes AFEU interrupt control register fields.
AFEU Interrupt Control Register (AFEUICR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Internal error. An internal processing error was detected while performing encryption.
0 Internal error enabled
1 Internal error disabled
Early read error. The AFEU register was read while the AFEU was performing encryption.
0 Early read error enabled
1 Early read error disabled
Context error. An AFEU key register, the key size register, data size register, mode register, or context
memory was modified while AFEU was performing encryption.
0 Context error enabled
1 Context error disabled
Key size error. A value outside the bounds 1–16 bytes was written to the AFEU key size register
0 Key size error enabled
1 Key size error disabled
Data size error. An inconsistent value was written to the AFEU data size register:
0 Data Size error enabled
1 Data size error disabled
Mode error. An illegal value was detected in the mode register.
0 Mode error enabled
1 Mode error disabled
Address error. An illegal read or write address was detected within the AFEU address space.
0 Address error enabled
1 Address error disabled
Output FIFO error. The AFEU output FIFO was detected non-empty upon write of AFEU data size register
0 Output FIFO non-empty error enabled
1 Output FIFO non-empty error disabled
Section 12.4.3.7, “AFEU Interrupt Status Register
Table 12-25. AFEU Interrupt Control Register Field Descriptions
—
Figure 12-27. AFEU Interrupt Control Register
Figure
12-27, controls the result of detected errors. For a given
50 51
IE ERE CE KSE DSE ME AE OFE IFE — IFO OFU —
1000
Description
52
53
54
(AFEUISR)”), if the corresponding
55
56
57
58
Freescale Semiconductor
59
Access: Read/Write
60
61
62
63