MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 167

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Refer to the MPC8533E Integrated Processor Hardware Specifications for the timing requirements for
HRESET assertion and negation.
The hard reset request output signal (HRESET_REQ) indicates to external logic that a hard reset is being
requested by hardware or software. Hardware causes this signal to assert for a boot sequencer failure (see
Section 11.4.5, “Boot Sequencer
e500 watchdog timer is configured to cause a reset request when it expires. Software may request a hard
reset by setting a bit in a global utilities register; see
4.4.2
The POR sequence for the MPC8533E is as follows:
Freescale Semiconductor
1. Power is applied to meet the specifications in the MPC8533E Integrated Processor Hardware
2. The system asserts HRESET and TRST, causing all registers to be initialized to their default states
3. The system applies a stable SYSCLK signal and stable PLL configuration inputs, and the device
4. System negates HRESET after its required hold time and after POR configuration inputs have been
5. MPC8533E enables I/O drivers.
6. The MPC8533E PCI interface can assert DEVSEL in response to configuration cycles.
7. The e500 PLL configuration inputs are applied, allowing the e500 PLL to begin locking to the
8. The CCB clock is cycled for approximately 50 μs to lock the e500 PLL.
9. The internal hard reset to the e500 core is negated and soft resets are negated to the PLLs and other
10. When PLL locking is completed, the boot sequencer is released, causing it to load configuration
Specifications.
and most I/O drivers to be three-stated (some clock, clock enabled, and system control signals are
active).
PLL begins locking to SYSCLK.
valid for at least 4 SYSCLK cycles.
device clock (the CCB clock).
remaining I/O blocks. The PLLs begin to lock.
data from serial ROMs, if enabled, as described in
Configuration.”
Power-On Reset Sequence
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
If the JTAG signals are not used, then TRST may be tied negated. It is
recommended that TRST not remain asserted after the negation of
HRESET. TRST may be connected directly to HRESET.
There is no need to assert the SRESET signal when HRESET is asserted. If
SRESET remains asserted upon negation of HRESET, the POR sequence
will be paused after the e500 core PLL is locked and before the e500 reset
is negated. The POR sequence will be resumed when SRESET is negated.
Mode,” and
Section 11.4.5.2, “EEPROM Data
NOTE:
Section 19.4.1.18, “Reset Control Register
Section 4.4.3.8, “Boot Sequencer
Reset, Clocking, and Initialization
Format”) or when the
(RSTCR).”
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