MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 499

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

needed. In this case the POINTER should be set to point directly at the first byte of the parcel, and the J
bit should be 0. On the other hand, if the data parcel is stored in several separate segments of memory, then
the scatter/gather capability is needed to assemble or distribute the complete parcel. In this case the
POINTER should be set to point to a link table, and the J bit should be 1. For link table format, see
Section 12.3.4, “Link Table Format.”
descriptor types, with the following exception(s):
12.3.4
Link tables implement scatter/gather capability. For gather operations, a link table specifies a list of
memory segments that are to be concatenated in the process of assembling data parcels. For scatter
operations, a link table specifies a list of memory segments into which the output data should be written.
Scatter or gather of a data parcel may be specified by a single link table or by a chain of link tables that are
linked together with pointers (see
The link table or chain of link tables accessed through some descriptor POINTER must specify enough
memory segments to hold all the data that will be accessed through that pointer. In most cases, only a single
data parcel is accessed through a given POINTER, and the chain of link tables specifies just that parcel. In
other cases, the descriptor POINTER is used multiple times to access a sequence of data parcels, and the
chain of link tables must supply data for the entire sequence. If a link table is used to access a sequence of
data parcels, the end of each parcel must also be at the end of a memory segment. In other words, a single
memory segment must not straddle two data parcels. An example of proper construction of link tables is
illustrated in
A link table may contain any number of long word entries. There are two kinds of entries, regular entries
and next entries. Each regular entry specifies a memory segment by means of a 36-bit starting address
(SEGPTR) and a 16-bit length (SEGLEN). A next entry is used at the end of a link table to specify that the
list of memory segments is continued in another link table. In a next entry, the N bit is set, the SEGPTR
field gives the address of the next link table, and the SEGLEN field must be 0. A chain of link tables may
contain any number of link tables.
Whether the list of memory segments is in a single link table or split into several link tables, the last entry
in the last link table is a regular entry with the R (return) bit set. The R bit signifies the end of link table
operations so that the channel returns to the descriptor for its next pointer (if any).
Link tables are illustrated in
Freescale Semiconductor
Field
•
0
The RAID-XOR descriptor type does not allow scatter/gather.
SEGLEN
Link Table Format
Figure
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
12-7.
15
16
Figure
—
Figure
12-7. A single link table entry is shown in
21
Scatter/gather capability is available for all pointer dwords of all
Figure 12-6. Link Table Entry
22
R
12-7).
23
N
24
—
27
28
EPTR
31
32
Figure
SEGPTR
Security Engine (SEC) 2.1
12-6.
12-21
63