MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 43

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Paragraph
Number
20.4.5
20.4.6
20.4.7
20.4.8
21.1
21.1.1
21.1.2
21.1.3
21.1.3.1
21.1.3.2
21.1.3.3
21.1.3.4
21.2
21.2.1
21.2.2
21.2.2.1
21.2.2.2
21.2.2.3
21.3
21.3.1
21.3.1.1
21.3.1.2
21.3.1.3
21.3.1.4
21.3.1.5
21.3.2
21.3.2.1
21.3.2.2
21.3.2.3
21.3.2.4
21.3.2.5
21.3.2.6
21.3.2.7
21.3.2.8
21.3.3
21.3.3.1
21.3.3.2
Freescale Semiconductor
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Introduction.................................................................................................................... 21-1
External Signal Description ........................................................................................... 21-5
Memory Map/Register Definition ................................................................................. 21-9
Triggering ................................................................................................................ 20-13
Burstiness Counting................................................................................................. 20-14
Performance Monitor Events ................................................................................... 20-16
Performance Monitor Examples .............................................................................. 20-28
Overview.................................................................................................................... 21-1
Features...................................................................................................................... 21-3
Modes of Operation ................................................................................................... 21-3
Overview.................................................................................................................... 21-5
Detailed Signal Descriptions ..................................................................................... 21-6
Watchpoint Monitor Register Descriptions ............................................................. 21-10
Trace Buffer Register Descriptions.......................................................................... 21-16
Context ID Registers................................................................................................ 21-23
Local Bus (LBC) Debug Mode.............................................................................. 21-4
DDR SDRAM Interface Debug Modes ................................................................. 21-4
Watchpoint Monitor Modes ................................................................................... 21-4
Trace Buffer Modes ............................................................................................... 21-4
Debug Signals—Details......................................................................................... 21-6
Watchpoint Monitor Trigger Signals—Details...................................................... 21-7
Test Signals—Details............................................................................................. 21-8
Watchpoint Monitor Control Registers 0–1 (WMCR0, WMCR1)...................... 21-10
Watchpoint Monitor Address Register (WMAR)................................................ 21-12
Watchpoint Monitor Transaction Mask Register (WMTMR) ............................. 21-14
Watchpoint Monitor Status Register (WMSR) .................................................... 21-16
Trace Buffer Control Registers (TBCR0, TBCR1) ............................................. 21-16
Trace Buffer Address Register (TBAR) .............................................................. 21-19
Trace Buffer Address Mask Register (TBAMR)................................................. 21-19
Trace Buffer Transaction Mask Register (TBTMR)............................................ 21-20
Trace Buffer Status Register (TBSR) .................................................................. 21-20
Trace Buffer Access Control Register (TBACR) ................................................ 21-21
Trace Buffer Access Data High Register (TBADHR)......................................... 21-22
Trace Buffer Access Data Register (TBADR)..................................................... 21-22
Programmed Context ID Register (PCIDR) ........................................................ 21-23
Current Context ID Register (CCIDR) ................................................................ 21-24
Watchpoint Monitor Address Mask Register (WMAMR) ................................. 21-14
Debug Features and Watchpoint Facility
Contents
Chapter 21
Title
Number
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