MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 592

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.6.5.7
The MCR, shown in
software to reset the SEC.
Table 12-62
12-114
22–23
24–30
32–39
40–47
0–21
Address 0x3_ 1030
Bits
31
Reset
Reset
W
W
R
R
CHN3_EU_PR_CNT Channel 3 EU priority counter. This counter is used by the controller to determine when
CHN4_EU_PR_CNT Channel 4 EU priority counter. This counter is used by the controller to determine when
32
0
CHN3_EU_PR_CNT
describes the master control register fields.
Master Control Register (MCR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Priority
Name
SWR
—
—
Figure
Table 12-62. Master Control Register (MCR) Field Descriptions
Reserved
Priority on master bus. The setting of these bits determines the transaction priority level the
SEC asserts to the MPC8533E internal arbiter. The SEC does not dynamically alter its priority
level based on system congestion or SEC utilization, however software may change the SEC
priority level in real-time.
00 Lowest priority (default)
01 Next lowest priority
10 Next highest priority
11 Highest priority
Reserved
Software reset. Writing 1 to this bit causes a global software reset. Upon completion of the
reset, this bit is automatically cleared.
0 Don’t reset
1 Global reset
Channel 3 has been denied access to a requested EU long enough to warrant immediate
elevation to top priority.
Note: If set to zero, the CHN4_EU_PR_CTR must also be set to zero, and the controller will
Channel 4 has been denied access to a requested EU long enough to warrant immediate
elevation to top priority.
Note: If set to zero, the CHN3_EU_PR_CTR must also be set to zero, and the controller will
12-85, controls certain functions in the controller and provides a means for
39 40
Figure 12-85. Master Control Register (MCR)
CHN4_EU_PR_CNT
assign EU’s on a pure round robin basis. If set to non-zero, CHN4_EU_PR_CTR must
also be set to a different, non-zero value.
assign EU’s on a pure round robin basis. If set to non-zero, CHN3_EU_PR_CTR must
also be set to a different, non-zero value.
—
47 48
All zeros
All zeros
CHN3_BUS_PR_CNT
Description
21
PRIORITY
22
23
55
24
56
CHN4_BUS_PR_CNT
Freescale Semiconductor
Access: User read/write
—
30
SWR
31
63