MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 113

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

The DDR controller offers an initialization bypass feature which system designers may use to prevent
re-initialization of main memory during system power-on following abnormal shutdown.
1.3.7
The programmable interrupt controller (PIC) implements the necessary functions to provide a flexible
solution for a general-purpose interrupt control. The interrupt controller unit implements the logic and
programming structures of the OpenPIC architecture. The MPC8533E interrupt controller unit supports its
processor core and provides for 12 external interrupts (with fully nested interrupt delivery), four message
interrupts, internal-logic driven interrupts, and four global high resolution timers. Up to 16 programmable
interrupt priority levels are supported.
The MPC8533E supports reception of interrupt messages from the PCI Express interfaces. The PIC
supports INTx and message shared interrupts (MSI) from the PCI Express interfaces. Four INTx interrupts
are presented as independent PIC interrupt sources. There are 256 individual MSI interrupt sources
supported as eight groups of 32 sources. Each of the eight groups constitutes an independent PIC interrupt
source. Individual interrupt sources have associated with them a vector, priority and destination value.
The interrupt controller unit can be bypassed to allow use of an external interrupt controller.
Inter-processor interrupt (IPI) communication is supported through the external interrupt and core reset
signals of different processor cores on the same device. The four IPIs are only used for self-interrupt in a
single-core device such as the MPC8533E.
1.3.8
The SEC is a modular and scalable security core optimized to process all the algorithms associated with
IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. Although it is not a protocol processor, the SEC is
designed to perform multi-algorithmic operations (for example, 3DES-HMAC-SHA-1) in a single pass of
the data, and every effort has been made to provide the SEC with the flexibility to perform single-pass
operations for current and emerging security protocols. The version of the SEC used in the MPC8533E is
specifically capable of performing single-pass security cryptographic processing for SSL 3.0, SSL
3.1/TLS 1.0, IPSec, SRTP, and IEEE Std. 802.11i ™.
Freescale Semiconductor
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This proposal precludes any other simultaneous use of IRQ_OUT.
Software based
The DDR controller also has a software-programmable bit that immediately puts main memory
into self-refresh mode.
It is expected that a critical interrupt routine triggered by an external voltage sense device will have
time to set this bit.
Programmable Interrupt Controller (PIC)
Integrated Security Engine (SEC) for the MPC8533E
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
The features described in this section are only available on the MPC8533E.
The MPC8533 does not include an integrated security engine.
NOTE
Overview
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