MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 643

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 14-16
14.3.1.11
The transfer error check disable register (LTEDR), shown in
checking. Note that control of error checking is independent of control of reporting of errors (LTEIR)
through the interrupt mechanism.
Freescale Semiconductor
10–11
13–31
Bits
Offset 0x0B4
3–4
6–7
Reset
12
0
1
2
5
8
9
W
R
BMD — PARD
ATMW Atomic error write
Name
ATMR Atomic error read
PAR
BM
WP
0
CS
—
—
—
—
—
describes LTESR fields.
1
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Bus monitor time-out
0 No local bus monitor time-out occurred.
1 Local bus monitor time-out occurred. No data beat was acknowledged on the bus within LBCR[BMT] × 8
Reserved
Parity
0 No local bus parity error
1 Local bus parity error. LTEATR[PB] indicates the byte lane that caused the error and LTEATR[BNK]
Reserved
Write protect error
0 No write protect error occurred.
1 A write was attempted to a local bus memory region that was defined as read-only in the memory controller.
Reserved
0 No atomic write error occurred.
1 The subsequent write (WARA) to a memory bank did not occur within 256 bus clock cycles.
0 No atomic read error occurred.
1 The subsequent read (RAWA) to a memory bank did not occur within 256 bus clock cycles.
Reserved
Chip select error
0 No chip select error occurred.
1 A transaction was sent to the LBC that did not hit any memory bank.
Reserved
Transfer Error Check Disable Register (LTEDR)
bus clock cycles from the start of a transaction.
indicates which memory controller bank was accessed.
Usually, in this case, a bus monitor time-out will occur (as the cycle is not automatically terminated).
2
Figure 14-14. Transfer Error Check Disable Register (LTEDR)
3
—
4
WPD
5
Table 14-16. LTESR Field Descriptions
6
—
7
WARA RAWA
8
9
All zeros
10 11
Description
—
CSD
Figure
12
13
14-14, is used to disable error
—
Access: Read/Write
Local Bus Controller
14-25
31