MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 654

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
14.4.1.6
Parity can be configured for any bank by programming BRn[DECC]. Parity is generated and checked on
a per-byte basis using LDP[0:3] for the bank if BRn[DECC] = 01 (normal parity) or BRn[DECC] = 10 for
read-modify-write (RMW) parity. Byte lane parity on LDP[0:3] is generated regardless of the BRn[DECC]
setting. Note that RMW parity can be used only for 32-bit port size banks. LBCR[EPAR] determines the
global type of parity (odd or even).
14.4.1.7
A bus monitor is provided to ensure that each bus cycle is terminated within a reasonable (user defined)
period. When a transaction starts, the bus monitor starts counting down from the time-out value
(LBCR[BMT]) until a data beat is acknowledged on the bus. It then reloads the time-out value and resumes
the countdown until the data tenure completes and then idles if there is no pending transaction. Setting
LTEDR[BMD] disables bus monitor error checking (i.e,. the LTESR[BM] bit is not set by a bus monitor
time-out); however, the bus monitor is still active and can generate a UPM exception (as noted in
Section 14.4.4.1.4, “Exception
It is very important to ensure that the value of LBCR[BMT] is not set too low; otherwise spurious bus
time-outs may occur during normal operation—particularly for SDRAMs— resulting in incomplete data
transfers. Accordingly, apart from the reset value of 0x00 (corresponding with the maximum time-out of
2048 bus cycles), LBCR[BMT] must not be set below 0x05 (or 40 bus cycles for time-out) under any
circumstances.
14.4.2
The GPCM allows a minimal glue logic and flexible interface to SRAM, EPROM, FEPROM, ROM
devices, and external peripherals. The GPCM contains two basic configuration register groups—BRn and
ORn.
Figure 14-23
mode. Byte-write enable signals (LWE) are available for each byte written to memory. Also, the output
enable signal (LOE) is provided to minimize external glue logic. On system reset, a global (boot)
chip-select is available that provides a boot ROM chip-select (LCS0) prior to the system being fully
configured.
14-36
During the reservation period, no other device can be granted access to the atomic bank. The
reservation is released when the device that created it accesses the same bank with a write
transaction. Additional read transactions prior to the releasing write are otherwise processed
normally and do not change the reservation status. If the device fails to release the reservation
within 256 bus clock cycles, the reservation is released and an atomic error is reported (if enabled).
General-Purpose Chip-Select Machine (GPCM)
shows a simple connection between an 8-bit port size SRAM device and the LBC in GPCM
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Parity Generation and Checking (LDP)
Bus Monitor
Requests”) or terminate a GPCM access.
Freescale Semiconductor