MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 213

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

5.12.3
For each of the counter registers, there are two corresponding local control registers. These two registers
specify which of the 128 available events is to be counted, what specific action is to be taken on overflow,
and various options for freezing a counter value under given modes or conditions.
5.13
This section provides an overview of the architectural differences and compatibilities of the e500 core
compared with the AIM Power Architecture technology. The two levels of the e500 programming
environment are as follows:
Like all devices that implement the Power Architecture technology, in general, the e500 core supports the
user-level architecture. The following sections are intended to highlight the main differences. For specific
implementation details refer to the relevant chapter.
5.13.1
The following sections generally describe the user and supervisor instruction sets.
5.13.1.1
The e500 core executes legacy user-mode binaries and object files except for the following:
Freescale Semiconductor
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PMLCa0–PMLCa3 provide fields that allow freezing of the corresponding counter in user mode,
supervisor mode, or under software control. Additionally, the overflow condition may be enabled
or disabled from this register. The contents of these registers are reflected to
UPMLCa0–UPMLCa3, which can be read from user mode with mfpmr.
PMLCb0–PMLCb3 provide count scaling for each counter register using configurable threshold
and multiplier values. The threshold is a 6-bit value and the multiplier is a 3-bit encoded value,
allowing eight multiplier values in the range of 1 to 128. Any counter may be configured to
increment only when an event occurs more than [threshold × multiplier] times. The contents of
these registers are reflected to UPMLCb0–UPMLCb3, which can be read from user mode with
mfpmr.
User level—This defines the base user-level instruction set, user-level registers, data types,
memory conventions, and the memory and programming models seen by application
programmers.
Supervisor level—This defines supervisor-level resources typically required by an operating
system, the memory management model, supervisor level registers, and the exception model.
The e500 supports vector and scalar single-precision floating-point operations as part of the SPE.
The e500v2 supports scalar double-precision floating-point instructions. These instructions have
different encoding than the AIM definition of the architecture. Additionally, the e500 core uses
GPRs for floating-point operations, rather than the FPRs defined by the UISA. Most porting of
floating-point operations can be handled by recompiling.
String instructions are not implemented on the e500; therefore, trap emulation must be provided to
ensure backward compatibility.
Legacy Support of Power Architecture Technology
Local Control Registers
Instruction Set Compatibility
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
User Instruction Set
Core Complex Overview
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