MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1088

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Express Interface Controller
Table 18-29
outbound transaction from an internal source.
PEX_ERR_CAP_R2 for the case when the error is caused by an inbound transaction from an external
source (that is, PEX_ERR_CAP_STAT[GSID] = 0h02 for controller 1), is shown in
Table 18-30
inbound transaction from an external source.
18.3.6.8
Together with the other PCI Express error capture registers, PEX_ERR_CAP_R3 allows vital error
information to be captured when an error occurs. Different error information is reported depending on
whether the error source is from an outbound transaction from an internal source or from an inbound
18-40
Offset 0xE30
Reset
0–31
W
Bit
R
0
Name
OD1
describes the fields of PEX_ERR_CAP_R2 for the case when the error is caused by an
describes the fields of PEX_ERR_CAP_R2 for the case when the error is caused by an
PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 18-33. PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)
0–31
Bits
Table 18-31. PCI Express Error Capture Register 2 Field Descriptions
Table 18-32. PCI Express Error Capture Register 2 Field Descriptions
Internal platform header bits 63-32. Contains the internal platform header bits 63–32. Note that this field
25–26
19-24
10-18
9
8
7
1-6
0
Name
GH2
is only valid for outbound internal platform errors. It is not valid for completion time-out errors
or PEX_CONFIG_ADDR/PEX_CONFIG_DATA errors. 27–31Transaction type (00000 for
write, 00001 for read)
Transaction priority
Source ID
Size
No snoop
Stash
Lock
Reserved
Address[0]
PCI Express 3rd DW (4-byte) header. This field contains the PCI
Express error packet’s 3rd DW (4-byte) header.
24–31
16–23
8–15
1–7
0
Internal Source, Outbound Transaction
External Source, Inbound Transaction
External Source, Inbound Transaction
Req ID[15:8]
Req ID[7:0]
Tag[7:0]
Lower Address[6:0]
Rsv
All zeros
GH2
Description
Description
Freescale Semiconductor
Figure
Access: Read/Write
18-31.
31