MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1295

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
0x5_1D00–
0x6_0000–
0x5_1CA0
0x5_1CB0
0x5_1CC0
0x5_1CD0
0x5_1CE0
0x5_1C20
0x5_1C30
0x5_1C40
0x5_1C50
0x5_1C60
0x5_1C70
0x5_1C80
0x5_1C90
0x5_1CF0
0x5_FFF0
0x6_0030
0x6_0040
0x6_0050
0x6_0060
0x6_0070
0x6_0080
0x6_0090
0x6_00A0
0x6_00B0
0xE_0000
0xE_0004
Offset
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MSIVPR1—Message shared interrupt vector/priority register
1
MSIDR1—Message shared interrupt destination register 1
MSIVPR2—Message shared interrupt vector/priority register
2
MSIDR2—Message shared interrupt destination register 2
MSIVPR3—Message shared interrupt vector/priority register
3
MSIDR3—Message shared interrupt destination register 3
MSIVPR4—Message shared interrupt vector/priority register
4
MSIDR4—Message shared interrupt destination register 4
MSIVPR5—Message shared interrupt vector/priority register
5
MSIDR5—Message shared interrupt destination register 5
MSIVPR6—Message shared interrupt vector/priority register
6
MSIDR6—Message shared interrupt destination register 6
MSIVPR7—Message shared interrupt vector/priority register
7
MSIDR7—Message shared interrupt destination register 7
Reserved
Reserved
IPIDR0—Interprocessor interrupt 0 (IPI 0) dispatch register
IPIDR1—Interprocessor interrupt 1 (IPI 1) dispatch register
IPIDR2—Interprocessor interrupt 2 (IPI 2) dispatch register
IPIDR3—Interprocessor interrupt 3 (IPI 3) dispatch register
CTPR—Current task priority register
WHOAMI—Who am I register
IACK—interrupt acknowledge register
EOI—End of interrupt register
PORPLLSR—POR PLL ratio status register
PORBMSR—POR boot mode status register
PIC Register Address Map—Per-CPU Registers
Table B-1. Memory Map (continued)
Register
Power-On Reset Configuration Values
Global Utilities Registers
Complete List of Configuration, Control, and Status Registers
Access
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
Mixed
R/W
—
—
W
W
R
R
R
R
0x1000_0000
0x0000_0001
0x1000_0000
0x0000_0001
0x1000_0000
0x0000_0001
0x1000_0000
0x0000_0001
0x1000_0000
0x0000_0001
0x1000_0000
0x0000_0001
0x1000_0000
0x0000_0001
0x0000_0000
0x0000_000F
0x0000_0000
0x0000_0000
0x0000_0000
0x00 nn _ n 0 nn
0x nnnn _0000
Reset
—
—
10.3.6.4/10-38
10.3.6.5/10-38
10.3.6.4/10-38
10.3.6.5/10-38
10.3.6.4/10-38
10.3.6.5/10-38
10.3.6.4/10-38
10.3.6.5/10-38
10.3.6.4/10-38
10.3.6.5/10-38
10.3.6.4/10-38
10.3.6.5/10-38
10.3.6.4/10-38
10.3.6.5/10-38
10.3.8.1/10-45
10.3.8.2/10-46
10.3.8.3/10-47
10.3.8.4/10-47
10.3.8.5/10-48
Section/Page
19.4.1.1/19-4
19.4.1.2/19-6
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B-37