MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1083

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

18.3.6.4
The PCI Express error capture status register, shown in
captured when an error occurs. Note that no further error capturing is performed until the ECV bit is
cleared.
Freescale Semiconductor
Offset 0xE20
Reset
24–31
W
Bits
R
15
16
17
18
19
20
21
22
23
0
CRSTD
IOIEPD
IACAD
CIEPD
OACD
Name
IOISD
IOIAD
MISD
CISD
Figure 18-27. PCI Express Error Capture Status Register (PEX_ERR_CAP_STAT)
—
PCI Express Error Capture Status Register (PEX_ERR_CAP_STAT)
Table 18-25. PCI Express Error Disable Register Field Descriptions (continued)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Invalid ATMU configuration access. When set will disable the setting of PEX_ERR_DR[IACA] bit.
1 Disable invalid ATMU configuration access detection
0 Enable invalid ATMU configuration access detection
CRS thresholded disable. When set will disable the setting of PEX_ERR_DR[CRST] bit.
1 Disable CRS threshold detection
0 Enable CRS threshold detection
Message invalid size disable. When set will disable the setting of PEX_ERR_DR[MIS] bit.
1 Disable invalid outbound message size detection
0 Enable invalid outbound message size detection
I/O invalid size disable. When set will disable the setting of PEX_ERR_DR[IOIS] bit.
1 Disable invalid outbound I/O size detection
0 Enable invalid outbound I/O size detection
Configuration invalid size disable. When set will disable the setting of PEX_ERR_DR[CIS] bit.
1 Disable invalid outbound configuration size detection
0 Enable invalid outbound configuration size detection
Configuration invalid EP disable. When set will disable the setting of PEX_ERR_DR[CIEP] bit.
1 Disable outbound configuration transaction EP mode detection
0 Enable outbound configuration transaction EP mode detection
I/O invalid EP disable. When set will disable the setting of PEX_ERR_DR[IOEP] bit.
1 Disable outbound I/O transaction EP mode detection
0 Enable outbound I/O transaction EP mode detection
Outbound ATMU crossing disable. When set will disable the setting of PEX_ERR_DR[OAC] bit.
1 Disable outbound crossing ATMU detection
0 Enable outbound crossing ATMU detection
I/O invalid address disable. When set will disable the setting of PEX_ERR_DR[IOIA] bit.
1 Disable greater than 4G I/O address detection
0 Enable greater than 4G I/O address detection
Reserved
—
All zeros
Figure
Description
18-27, allows vital error information to be
24
PCI Express Interface Controller
TO
25
26
GSID
Access: Mixed
30
18-35
ECV
w1c
31