MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1311

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Index
DEAR (data exception address register), see e500 core,
Debug modes
DEC (decrementer register), see e500 core, registers
DECAR (decrementer auto-reload register), see e500 core,
DMA channel 2 and 3 signal select, 19-13
DMA controller
Freescale Semiconductor
self-refresh
signals summary, 9-3
and watchpoint monitor signals summary, 21-5
and watchpoint monitor/trace buffer block diagram, 21-1
DDR signal selection (POR)
DDR source ID debug modes, 21-4, 21-25
DDR/LBC signal selection (POR), 4-20
e500 core registers, 6-39–6-45
features, 21-3
functional description, 21-25
LBC source ID debug mode, 14-4, 21-4, 21-25
memory map/register definition, 21-9
modes of operation (set at POR), 21-3
overview, 21-1
PCI/PCI-X
performance monitor events, 20-27
POR status (global utilities), 19-10
READY negation, 4-2
software debug
trace buffer, see Trace buffer
watchpoint, see Watchpoint monitor
block diagram, 16-1
channel operation, 16-25
descriptor formats, 16-34
error handling, 16-33
features, 16-2
functional description, 16-25
interrupts, 16-10–16-13, 16-15, 16-20, 16-24, 16-33
limitations and restrictions, 16-37
memory map/register definition, 16-6
write timing adjustments, 9-59
operation in sleep mode, 9-63
using forced mode for battery backup, 9-72
see also Signals, DDR
registers
see also Signals, debug
ECC pins used for debug, 4-20
source ID on debug signals, 21-26
source ID on ECC pins, 21-26
source ID debug mode, 21-25
context ID registers, 21-23
registers
bandwidth control, 16-32
channel abort, 16-32
channel state, 16-32
stride size and distance, 16-33
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
DMA_DACK [0:3] (DMA acknowledge) signals, 16-6
DMA_DDONE[0:3] (DMA done) signals, 16-6
DMA_DREQ[0:3] (DMA request) signals, 16-6
Doze mode, 1-20, 19-28
DUART
modes of operation, 16-2
overview, 16-2
performance monitor events, 20-18
register descriptions, 16-9–16-25
signal select—channel 2 and 3, 19-13, 19-33
signals summary, 16-5
system considerations, 16-38
transfer interfaces, 16-33
see also Global utilities, power management
asynchronous communication bits, 13-1
baud-rate generator logic, 13-21
block diagram, 13-2
divisor latch access bit (ULCRn[DLAB]), 13-4, 13-12
error handling, 13-22
errors detected, 13-2
features, 13-1
functional description, 13-19
initialization/application information, 13-24
basic mode transfer, 16-26
channel continue mode for cascading transfer chains,
extended DMA mode transfer, 16-28
external control mode transfer, 16-30
by acronym, see Register Index
see also Signals, DMA controller
unusual scenarios, 16-40
parity bit, 13-21
START bit, 13-20
STOP bit, 13-21
framing error, 13-9, 13-15, 13-21, 13-22
overrun error, 13-22
parity error, 13-22
basic chaining mode, 16-27
basic chaining single-write start mode, 16-28
basic direct mode, 16-26
basic direct single-write start mode, 16-26
basic channel continue mode, 16-31
extended mode, 16-32
extended chaining mode, 16-29
extended chaining single-write start mode, 16-29
extended direct mode, 16-28
extended direct single-write start mode, 16-28
DMA to configuration and control registers, 16-40
DMA to DUART, 16-41
DMA to e500 core, 16-40
DMA to Ethernet, 16-40
DMA to I2C, 16-40
16-31
Index-3
D–D