MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1316

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

I–I
IACn (instruction address compare registers 1–2), see e500
Initialization
Index-8
interrupts
memory map/register definition, 11-4
modes of operation, 11-2
overview, 11-2
register descriptions, 11-5
signals summary, 11-3
transaction protocol, 11-11
DDR (initialization and application information), 9-68
ECM (initialization and application information),
eTSEC (initialization and application information),
I
2
C interface (initialization and application information),
repeated START generation, 11-23
START generation, 11-12, 11-22
STOP generation, 11-13, 11-23
calling address match condition, 11-6
flowchart for interrupt service routine, 11-24
interrupt after transfer, 11-22
interrupt enable bit (I2CCR[MIEN]), 11-8
interrupt on START, 11-22
interrupt pending status bit (I2CSR[MIF]), 11-10
interrupt-driven byte-to-byte transfers, 11-2
read of last byte, 11-23
slave mode interrupt service routine guidelines, 11-23
boot sequencer mode, 11-2, 11-17–11-20
interrupt-driven byte-to-byte data transfer, 11-2
master mode, 11-2
slave mode, 11-2
by acronym, see Register Index
see also Signals, I
handshaking, 11-16
repeated START condition, 11-3, 11-13
slave address transmission, 11-12
START condition, 11-3, 11-12, 11-22
STOP condition, 11-3, 11-13, 11-23
core, registers
programming different memory types, 9-69
see also eTSEC, configuration
boot sequencer mode, see I
generation of SCL when SDA low, 11-23
initialization sequence, 11-21
post-transfer software response, 11-22
repeated START generation, 11-23
START generation, 11-12, 11-22
STOP generation, 11-13, 11-23
for slave transmitter routine, 11-24
loss of arbitration, 11-24
8-10–8-11
15-141, 15-180–15-206
11-21–11-25
mode
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
C
2
C interface, boot sequencer
Intel PC133 SDRAM commands (LBC), 14-49
Interrupt controller (PIC)
LBC (initialization and application information),
LBC SDRAM power-on initialization, 14-48
PCI/PCI-X (initialization and application information),
PIC (initialization and application information), 10-52
watchpoint monitor and trace buffer, 21-31
block diagram, 10-47
configuration (global), 10-19
critical interrupts, 10-6, 10-27, 10-30, 10-39
destination (interrupt routing), 10-39
end of interrupt (EOI), 10-47, 10-49
external interrupts
features, 10-3
flow (interrupt processing), 10-47
functional description, 10-47
global timers, 10-22, 10-51
initialization/application information, 10-52
interrupt acknowledge (IACK) signaling, 10-46, 10-49
interrupt routing (mixed mode), 10-6, 10-47
interrupt source priorities, 10-49
memory map/register definition, 10-9
messaging interrupts, 10-50
modes of operation, 10-4, 10-19
nesting of interrupts, 10-50
overview, 1-15, 10-1
performance monitor events, 20-20
power management (wake up conditions), 10-3
processor core interrupt sources, 10-3
processor current task priority, 10-49
programming guidelines, 10-52
register descriptions, 10-17
IRQ_OUT, 10-6
see also e500 core, critical interrupts
routed to critical interrupt (cint), 10-30
routed to IRQ_OUT, 10-28
cascading of timers, 10-25, 10-27
clocking of timers, 10-23, 10-27
RTC (real time clock) signal options, 4-3, 4-23, 10-25,
mixed mode, 10-4
pass-through mode (to support external interrupt
critical interrupt (cint) sources, 10-27
changing interrupt source configuration, 10-54
by acronym, see Register Index, 10-17
global registers, 10-17–10-22
global timer registers, 10-22–10-27
interrupt source configuration registers, 10-22–10-25,
14-79–14-112
17-67–17-70
10-26
controllers), 10-5
10-38–10-43
Freescale Semiconductor
Index