MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 755

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Some of the error interrupts are independently counted in the MIB block counters. Software may choose
to mask off these interrupts because these errors are visible to network management via the MIB counters.
Figure 15-4
Table 15-7
Freescale Semiconductor
Offset eTSEC1:0x2_4010; eTSEC3: 0x2_6010
Reset
Reset
Bits
0
1
2
3
4
5
W
W
R BABR
R RXB
— Operational diagnostics are events on: GTSC, GRSC, TXC and RXC
— Interrupts resulting from errors/problems detected in the network or transceiver are: BABR,
— Interrupts resulting from internal errors are: FIR, FIQ, DPE, PERR, EBERR, TXE, XFUN and
w1c
w1c
16
0
EBERR Internal bus error. This bit indicates that a system bus error occurred while a DMA transaction was
MSRO
Name
BABR
RXC
BSY
—
BABT, LC and CRL
BSY
describes the fields of the IEVENT register.
describes the definition for the IEVENT register.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
RXC
w1c
17
1
maximum frame length register while MACCFG2[Huge Frame] is set.
0 Excessive frame not received.
1 Excessive frame received.
Receive control interrupt. A control frame was received while MACCFG1[Rx_Flow] is set. As soon as the
transmitter finishes sending the current frame, a pause operation is performed.
0 Control frame not received.
1 Control frame received.
0 No frame received and discarded.
1 Frame received and discarded.
underway. As a result, transferred data is expected to be partially or completely invalid.
0 No system bus error occurred.
1 System bus error occurred.
Reserved
size of its register.
0 MIB count not exceeding its register size.
1 MIB count exceeds its register size.
Babbling receive error. This bit indicates that a frame was received with length in excess of the MAC’s
Busy condition interrupt. Indicates that a frame was received and discarded due to a lack of buffers.
MIB counter overflow. This interrupt is asserted if the count for one of the MIB counters has exceeded the
BSY
w1c
18
2
—
EBERR
w1c
19
3
Figure 15-4. IEVENT Register Definition
Table 15-7. IEVENT Field Descriptions
MAG MMRD MMWR GRSC RXF
w1c
—
20
4
MSRO
w1c
w1c
21
5
GTSC
w1c
w1c
All zeros
All zeros
22
6
Description
BABT TXC TXE TXB TXF
w1c
w1c
23
7
w1c
w1c
24
8
Enhanced Three-Speed Ethernet Controllers
w1c
25
9
w1c w1c
—
10
26
11
27
w1c w1c w1c
FIR FIQ DPE PERR
—
12
28
w1c w1c
LC CRL XFUN
13
29
Access: w1c
14
30
w1c
w1c
15-25
15
31