MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 583

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

(MCR)
will implement the weighted priority scheme. If both are zero, the arbitration will be round-robin. Setting
only one of the CHN_EU_PR_CNT fields to a non-zero value will result in unpredictable operation.
12.6.1.1
When arbitrating on the priority scheme, the priority is as follows:
Initially, the priority is channel 1, channel 2, channel 3, and channel 4, in that order. In order to prevent
channels 3 and 4 from being locked out, the CHN3_EU_PR_CNT and CHN4_EU_PR_CNT fields are
implemented in the master control register (MCR). The value of these fields determines how many times
channel 3 or channel 4 can be refused access to an EU in favor of a higher priority channel. A counter is
implemented in the arbiter for each of these entities. When the channel has lost arbitration the number of
times specified in its CHN_EU_PR_CNT field, then that channel has the 2nd highest priority when the
requested EU becomes available. CHN1 always has the highest priority, but it cannot make back to back
requests, so the 2nd highest priority channel will be serviced upon completion of the current CHN1
operation.
It is permissible for the CHN_EU_PR_CNT values to be different from the CHN_BUS_PR_CNT values,
i.e., EU access may be prioritized, while bus access is pure round robin, and vice-versa.
12.6.1.2
In round-robin arbitration, requesting channels are granted access in rotating numerical order: 1, 2, 3, 4, 1,
2, ... etc.
12.6.2
The controller in the SEC has the ability to be a bus master or a slave. This means that the controller can
issue read and write commands to the bus, and it can also be written to and read from by the host.
The controller is the sole bus master within the SEC. All other modules are slave-only devices. A channel
may request access to system resources including the bus. In these cases, the channel must provide the
starting address of the transfer for the bus(es) requested. All subsequent addresses are generated by the
controller. All addresses are sequential.
The controller is involved in transfers on the internal system bus and the internal bus. For
channel-controlled access, the channels make requests to the controller to perform data transfers. The
channel specifies data lengths and addresses for the internal and system buses. Multiple channels may
request use of the controller at the same time, so the controller performs arbitration to choose a channel.
The controller then services the request and performs the required transfer. Most transfers involve not only
Freescale Semiconductor
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Channel 1—Highest priority
Channel 2—Second highest priority, unless CHN3_EU_PR_CNT or CHN4_EU_PR_CNT expired
Channel 3—Third priority, unless CHN4_EU_PR_CNT expired
Channel 4—Lowest priority, until CHN4_EU_PR_CNT expired
. If both CHN3_EU_PR_CNT and CHN4_EU_PR_CNT are set to non-zero values, the arbiter
Bus Transfers
Channel Priority Arbitration
Channel Round-Robin Arbitration
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Security Engine (SEC) 2.1
12-105