MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 938

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DMA Controller
16.1.2
The DMA controller has four high-speed DMA channels. Both the e500 core and external devices can
initiate DMA transfers. All channels are capable of complex data movement and advanced transaction
chaining.
fetches and block transfers are initiated by each channel. A channel is selected by the arbitration logic and
information is passed to the source and destination control blocks for processing. The source and
destination blocks generate read and write requests to the address tenure engine, which manages the DMA
master port address interface. After a transaction is accepted by the master port, control is transferred to
the data tenure engine that manages the read and write data transfers. A channel remains active in the
shared resources for the duration of the data transfer unless the allotted bandwidth per channel is reached.
16.1.3
The DMA controller offers the following features:
16.1.4
The MPC8533E has two modes of operation: basic and extended. Basic mode is the DMA legacy mode.
It does not support advanced features. Extended mode supports advanced features like striding and flexible
descriptor structures.
These two basic modes allow users to initiate and end DMA transfers in various ways.
summarizes the relationship between the modes and the following features:
16-2
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Four high-speed/high-bandwidth channels accessible by local and remote masters
Basic DMA operation modes (direct, simple chaining)
Extended DMA operation modes (advanced chaining and stride capability)
Cascading descriptor chains
Misaligned transfers
Programmable bandwidth control between channels
Up to 256 bytes for DMA sub-block transfers to maximize performance
Three priority levels supported for source and destination transactions
Interrupt on error and completed segment, list, or link
Externally-controlled transfer using DMA_DREQ, DMA_DACK, and DMA_DDONE
Direct mode. No descriptors are involved. Software must initialize the required fields as described
in
Chaining mode. Software must initialize descriptors in memory and the required fields as described
in
Single-write start mode. The DMA process can be started by using a single-write command to
either the descriptor address register in one of the chaining modes or the source/destination address
registers in one of the direct modes.
External control capability. This allows an external agent to start, pause, and check the status of a
DMA transfer which has already been initialized.
Figure 16-1
Table 16-1
Table 16-1
Overview
Features
Modes of Operation
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
before starting a transfer.
before starting a transfer.
is a high-level block diagram of the DMA controller. Operations such as descriptor
Freescale Semiconductor
Table 16-1