MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 629

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 14-4
Freescale Semiconductor
17–18
19–20
21–22
24–26
28–29
0–16
Bits
23
27
30
31
DECC Specifies the method for data error checking.
Name
MSEL Machine select. Specifies the machine to use for handling memory operations.
ATOM Atomic operation. Writes (reads) to the address space handled by the memory controller bank reserve the
XBA
WP
BA
PS
—
—
V
describes BRn fields.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Base address. The upper 17 bits of each base register are compared to the address on the address bus to
determine if the bus master is accessing a memory bank controlled by the memory controller. Used with the
address mask bits OR n [AM].
Extended base address. Extends BA by a further 2 bits such that 19 bits of each base register are compared
to the 34-bit transaction address. XBA provides the extra 2 msb’s (i.e. {XBA,BA} represents the full base
address). Used with the extended address mask bits OR n [XAM].
Port size. Specifies the port size of this memory region. For BR0, PS is configured from the boot ROM location
signals during reset. For all other banks the value is reset to 00 (port size not defined).
00 Reserved
01 8-bit
10 16-bit
11 32-bit
00 Data error checking disabled, but normal parity generation
01 Normal parity generation and checking
10 Read-modify-write parity generation and normal parity checking (32-bit port size only)
11 Reserved
Write protect
0 Read and write accesses are allowed.
1 Only read accesses are allowed. The memory controller does not assert LCS n on write cycles to this
000 GPCM (reset value)
001 Reserved
010 Reserved
011 SDRAM
100 UPMA
101 UPMB
110 UPMC
111 Reserved
Reserved
selected memory bank for the exclusive use of the accessing device. The reservation is released when the
device performs a read (write) operation to this memory controller bank. If a subsequent read (write) request
to this memory controller bank is not detected within 256 bus clock cycles of the last write (read), the
reservation is released and an atomic error is reported (if enabled).
00 The address space controlled by this bank is not used for atomic operations.
01 Read-after-write-atomic (RAWA)
10 Write-after-read-atomic (WARA)
11 Reserved
Reserved
Valid bit. Indicates that the contents of the BR n and OR n pair are valid. LCS n does not assert unless V is set
(an access to a region that has no valid bit set may cause a bus time-out). After a system reset, only BR0[V]
is set.
0 This bank is invalid.
1 This bank is valid.
memory bank. LTESR[WP] is set (if WP is set) if a write to this memory bank is attempted, and a local bus
error interrupt is generated (if enabled), terminating the cycle.
Table 14-4. BR n Field Descriptions
Description
Local Bus Controller
14-11