mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1027

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

42.3.2 I2C Frequency Divider register (I2Cx_F)
Addresses: I2C0_F is FFFF_81C0h base + 1h offset = FFFF_81C1h
Freescale Semiconductor, Inc.
MULT
Reset
Field
ICR
Read
7–6
5–0
Write
Bit
I2C1_F is FFFF_81D0h base + 1h offset = FFFF_81D1h
I2C2_F is FFFF_81E0h base + 1h offset = FFFF_81E1h
I2C3_F is FFFF_81F0h base + 1h offset = FFFF_81F1h
The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate
the I2C baud rate.
00
01
10
11
Clock rate
Prescales the bus clock for bit rate selection. This field and the MULT field determine the I2C baud rate,
the SDA hold time, the SCL start hold time, and the SCL stop hold time. For a list of values corresponding
to each ICR setting, see
The SCL divider multiplied by multiplier factor (mul) determines the I2C baud rate.
I2C baud rate = bus speed (Hz)/(mul × SCL divider)
The SDA hold time is the delay from the falling edge of SCL (I2C clock) to the changing of SDA (I2C
data).
SDA hold time = bus period (s) × mul × SDA hold value
The SCL start hold time is the delay from the falling edge of SDA (I2C data) while SCL is high (start
condition) to the falling edge of SCL (I2C clock).
SCL start hold time = bus period (s) × mul × SCL start hold value
The SCL stop hold time is the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
data) while SCL is high (stop condition).
SCL stop hold time = bus period (s) × mul × SCL stop hold value
7
0
MULT
mul = 1
mul = 2
mul = 4
Reserved
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
I2C Divider and Hold
I2Cx_F field descriptions
0
5
Preliminary
0
4
Values.
Description
0
3
ICR
Chapter 42 Inter-Integrated Circuit (I2C)
0
2
0
1
0
0
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