mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 642

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Register Definition
29.3.4 ADC data result register (ADCx_Rn)
The data result registers (Rn) contain the result of an ADC conversion of the channel
selected by the corresponding status and channel control register (SC1A:SC1n). For
every status and channel control register, there is a corresponding data result register.
Unused bits in the Rn register are cleared in unsigned right justified modes and carry the
sign bit (MSB) in sign extended 2's complement modes.
The following table describes the behavior of the data result registers in the different
modes of operation.
642
12-bit single-
ended
10-bit single-
ended
8-bit single-
ended
Conversion
ADLSTS
mode
Field
1–0
S: Sign bit or sign bit extension;
D: Data (2's complement data if indicated)
ADHSC configures the ADC for very high speed operation. The conversion sequence is altered (2 ADCK
cycles added to the conversion time) to allow higher speed conversion clocks.
0
1
Long sample time select
ADLSTS selects between the extended sample times when long sample time is selected (ADLSMP=1).
This allows higher impedance inputs to be accurately sampled or to maximize conversion speed for lower
impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
00
01
10
11
0
0
0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Normal conversion sequence selected.
High speed conversion sequence selected (2 additional ADCK cycles to total conversion time).
Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total).
12 extra ADCK cycles; 16 ADCK cycles total sample time.
6 extra ADCK cycles; 10 ADCK cycles total sample time.
2 extra ADCK cycles; 6 ADCK cycles total sample time.
0
0
0
Table 29-35. Data result register description
0
0
0
ADCx_CFG2 field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
0
0
0
D
0
0
D
0
0
Preliminary
D
D
0
NOTE
D
D
0
Description
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Freescale Semiconductor, Inc.
D
D
D
D
D
D
Unsigned right
justified
Unsigned right
justified
Unsigned right
justified
Format