mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 729

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

33.1.6 Modes of Operation
PDB ADC trigger operates in the following modes.
Disabled: Counter is off and all pre-trigger and trigger outputs are low.
Enabled One-Shot: Counter is enabled and restarted at count zero upon receiving a
positive edge on the selected trigger input source or software trigger is selected and
SC[SWTRIG] is written with 1. In each PDB channel, an enabled pre-trigger asserts once
per trigger input event; the trigger output asserts whenever any of pre-triggers is asserted.
Enabled Continuous: Counter is enabled and restarted at count zero. The counter is
rolled over to zero again when the count reaches the value specified in the modulus
register, and the counting is restarted. This enables a continuous stream of pre-triggers/
trigger outputs as a result of a single trigger input event.
Enabled Bypassed: The pre-trigger and trigger outputs assert immediately after a
positive edge on the selected trigger input source or software trigger is selected and
SC[SWTRIG] is written with 1, that is the delay registers are bypassed. It is possible to
bypass any one or more of the delay registers; therefore this mode can be used in
conjunction with One-Shot or Continuous mode.
33.2 PDB Signal Descriptions
This table shows the detailed description of the external signal.
33.3 Memory Map and Register Definition
Freescale Semiconductor, Inc.
EXTRG
Signal
External trigger input source. If the PDB is enabled and external trigger
input source is selected, a positive edge on the EXTRG signal resets and
starts the counter.
Description
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table 33-1. PDB Signal Descriptions
Preliminary
Chapter 33 Programmable Delay Block (PDB)
I/O
I
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