mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 70

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

MCF51JF Feature Summary
70
Flash write voltage
Packages
Temperature range, ambient (T
Temperature range, junction (T
Central processing unit (CPU)
Maximum CPU frequency
Dhrystone 2.1 performance
Interrupt controller (INTC)
Direct memory access (DMA) controller
Low-leakage wakeup unit (LLWU)
Debug
Power management controller (PMC)
3.3 V voltage regulator (VREG)
Total flash memory
Program flash
Feature
J
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Table 2-1. Feature Summary (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Down to 1.71 V
32-pin QFN (5 x 5 mm
44-pin Laminate QFN (5 x 5 mm
48-pin LQFP (7 x 7 mm
64-pin Laminate QFN (9 x 9 mm
64-pin LQFP (10 x 10 mm
-40°C to 105°C (V temperature)
-40°C to 125°C
High-performance Version 1 (V1) ColdFire core with EMAC and DIV hardware
acceleration
Implements instruction set revision C (ISA_C)
50 MHz
1.10 DMIPS per MHz performance when executing from internal RAM
0.99 DMIPS per MHz when executing from flash
Supports 7 priority levels and software interrupt acknowledges
Four independently programmable channels provide the means to transfer data
directly between system memory and I/O peripherals
16 external wakeup pins with digital glitch filter
4 internal wakeup sources
RESET pin can be treated as reset wakeup in low leakage (LLS and VLLS)
modes
Integrated ColdFire DEBUG_Rev_B+ interface with single wire BDM
Real-time debug support, with six hardware breakpoints that can be configured
to halt the processor or generate debug interrupt
Capture of compressed processor status and debug data into trace buffer
On-chip trace buffer that provides programmable start/stop recording conditions
Various stop, wait, and run modes to enable low power applications:
Peripheral clock enable register can disable clocks to unused modules, further
reducing current consumption
Low voltage warning and detect with selectable trip points
5 V input, 3.3 V output, up to 120 mA
Up to 160 KB (128 KB + 32 KB)
Up to 128 KB
Table continues on the next page...
Memory and Memory Interfaces
• Run and stop regulation modes to enable low power MCU operation
• Several low power and low leakage stop modes
Power Management
Core and System
Preliminary
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Details
Freescale Semiconductor, Inc.