mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 111

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

3.8.1.5 ADC Reference, Triggers, and Alternate Clock
ADC Reference
Select the reference on the ADC using the ADC's SC2[REFSEL] field. The available
options are:
ADC Triggers
In addition to the PDB, the LPTMR0 module is connected to the ADC as a trigger source.
LPTMR0 can trigger the ADC in low power modes where the PDB does not work.
Triggering by the LPTMR0 module allows the ADC to perform conversion in a low
power mode and store the output in the result register. When the data is ready in the result
register, the ADC generates an interrupt that will wake the system from low power mode.
Select the trigger source for the ADC using the SIM's SOPT7[ADTRGS] bit.
Alternate Clock
The ADC's alternate clock is connected to the XOSC2's ERCLK.
3.8.1.6 Clock Gating
The clock to the ADC module can be gated on and off using the SIM's SCGCx[ADC] bit.
This bit is cleared after any reset, which disables the clock to the module to conserve
power. Before initializing the ADC, set the SCGCx[ADC] bit to enable the clock.
Freescale Semiconductor, Inc.
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ADC Channel (ADCH)
• VREFH/VREFL - connected as the primary reference option
• 1.2 V VREFO - connected as the V
• PDB trigger (run mode)
• LPTMR0 overflow (can work in stop mode)
The clock to the ADC cannot be gated during an active
conversion.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
AD30
AD31
Channel
ALT
Preliminary
NOTE
reference option
VREFL
Module disabled
Input
Chapter 3 Chip Configuration
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