mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 731

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

33.3.1 Status and Control Register (PDBx_SC)
Addresses: PDB0_SC is FFFF_8540h base + 0h offset = FFFF_8540h
Freescale Semiconductor, Inc.
Reset
Reset
Bit
Bit
W
W
Reserved
SWTRIG
R
R
PDBEIE
LDMOD
31–20
19–18
Field
17
16
31
15
0
0
30
14
0
0
PRESCALER
This read-only bitfield is reserved and always has the value zero.
Load Mode Select
Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers, after 1 is written to
LDOK.
00
01
10
11
PDB Sequence Error Interrupt Enable
This bit enables the PDB sequence error interrupt. When this bit is set, any of the PDB channel sequence
error flags generates a PDB sequence error interrupt.
0
1
Software Trigger
PDB sequence error interrupt disabled.
PDB sequence error interrupt enabled.
29
13
The internal registers are loaded with the values from their buffers immediately after 1 is written to
LDOK.
The internal registers are loaded with the values from their buffers when the PDB counter reaches
the MOD register value after 1 is written to LDOK.
The internal registers are loaded with the values from their buffers when a trigger input event is
detected after 1 is written to LDOK.
The internal registers are loaded with the values from their buffers when either the PDB counter
reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.
0
0
28
12
0
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
27
11
0
0
PDBx_SC field descriptions
Table continues on the next page...
26
10
TRGSEL
0
0
0
25
0
0
9
Preliminary
24
0
0
8
Description
23
0
0
7
22
0
0
6
Chapter 33 Programmable Delay Block (PDB)
21
0
0
5
20
0
0
0
4
19
0
0
3
LDMOD
MULT
18
0
0
2
17
0
0
1
16
0
0
0
0
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