mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1276

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Descriptions
1276
L2EPC
L1EBL
L2PCI
L1ED
12–6
Field
L1DI
L2T
L1T
17
16
15
14
13
5
Enable Level 2 PC Breakpoint
0
1
Level 2 PC Breakpoint Invert
0
1
Level 2 Trigger
Determines the logic operation for the trigger between the PC_condition and the (Address_range
and Data_condition) condition where the inclusion of a Data_condition is optional. The debug
architecture supports the creation of single- or double-level triggers.
0
1
Level 1 Trigger
Determines the logic operation for the trigger between the PC_condition and the (Address_range
and Data_condition) condition where the inclusion of a Data_condition is optional. The debug
architecture supports the creation of single- or double-level triggers.
0
1
Enable Level 1 Breakpoints
Global enable for the level 1 breakpoint triggers.
0
1
Enable Level 1 Data Breakpoint
Setting an L1ED bit enables the corresponding data breakpoint condition based on the size and
placement on the processor’s local data bus. Clearing all ED bits disables data breakpoints.
Bit
28
27
26
25
24
23
22
Level 1 Data Breakpoint Invert
Inverts the logical sense of all the data breakpoint comparators. This can develop a trigger based
on the occurrence of a data value other than the DBR contents.
0
1
Description
Table 50-23. TDR Field Descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Disable
Enable
Do not invert
Invert
Trigger = PC_condition && (Address_range && Data_condition)
Trigger = PC_condition || (Address_range && Data_condition)
Trigger = PC_condition && (Address_range && Data_condition)
Trigger = PC_condition || (Address_range && Data_condition)
Disable all level 1 breakpoints
Enable all level 1 breakpoints
Description
Data longword. Entire processor's local data bus
Lower data word
Upper data word
Lower lower data byte. Low-order byte of the low-order word
Lower middle data byte. High-order byte of the low-order word
Upper middle data byte. Low-order byte of the high-order word
Upper upper data byte. High-order byte of the high-order word
Do not invert
Invert
Table continues on the next page...
Preliminary
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