mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 255

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 11 Core
If the processor is not in trace mode and executes a stop instruction where the immediate
operand sets SR[T], hardware loads the SR and generates a trace exception. The PC in
the exception stack frame points to the instruction after the stop, and the SR reflects the
value loaded in step 2.
Because ColdFire processors do not support any hardware stacking of multiple
exceptions, it is the responsibility of the operating system to check for trace mode after
processing other exception types. As an example, consider a TRAP instruction execution
while in trace mode. The processor initiates the trap exception and then passes control to
the corresponding handler. If the system requires that a trace exception be processed, it is
the responsibility of the trap exception handler to check for this condition (SR[T] in the
exception stack frame set) and pass control to the trace handler before returning from the
original exception.
11.3.3.7 Unimplemented Line-A Opcode
The default operation of the V1 ColdFire processor is the generation of an illegal opcode
reset event if an unimplemented line-A opcode is detected. If CPUCR[IRD] is set, the
reset is disabled and a processor exception is generated as detailed below.
A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is
generated by the attempted execution of an undefined line-A opcode.
11.3.3.8 Unimplemented Line-F Opcode
The default operation of the V1 ColdFire processor is the generation of an illegal opcode
reset event if an unimplemented line-F opcode is detected. If CPUCR[IRD] is set, the
reset is disabled and a processor exception is generated as detailed below.
A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is
generated when attempting to execute an undefined line-F opcode.
11.3.3.9 Debug Interrupt
See the debug chapter for a detailed explanation of this exception, which is generated in
response to a hardware breakpoint register trigger. The processor does not generate an
IACK cycle, but rather calculates the vector number internally (vector number 12).
Additionally, SR[M,I] are unaffected by the interrupt.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
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