mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1162

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional description
44.4.1.2 Bit Clock
The SAI transmitter and receiver support asynchronous free running bit clocks that can
be generated internally from an audio master clock or supplied externally. There is also
the option for synchronous bit clock and frame sync operation between the receiver and
transmitter or between multiple SAI peripherals.
Externally generated bit clocks should be enabled before the SAI transmitter or receiver
is enabled and should be disabled after the SAI transmitter or receiver is disabled and
they have completed their current frames.
44.4.1.3 Bus Clock
The bus clock is used by the control and configuration registers and to generate
synchronous interrupts and DMA requests.
44.4.2 SAI resets
The SAI is asynchronously reset on system reset. The SAI has a software reset and a
FIFO reset.
44.4.2.1 Software reset
The SAI transmitter includes a software reset that resets all transmitter internal logic,
including the bit clock generation, status flags and FIFO pointers. It does not reset the
configuration registers. The software reset remains asserted until cleared by software.
The SAI receiver includes a software reset that resets all receiver internal logic, including
the bit clock generation, status flags and FIFO pointers. It does not reset the configuration
registers. The software reset remains asserted until cleared by software.
44.4.2.2 FIFO reset
The SAI transmitter includes a FIFO reset that synchronizes the FIFO write pointer to the
same value as the FIFO read pointer. This empties the FIFO contents and is to be used
after the Transmit FIFO Error Flag is set, and before the FIFO is re-initialized and the
Error Flag is cleared. The FIFO Reset is asserted for one cycle only.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
1162
Freescale Semiconductor, Inc.