mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 400

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
An asserted RESET pin will cause an exit from LLS mode returning the device to normal
RUN mode. When LLS is exiting via the RESET pin, the PIN and WAKEUP bits are set
in the SRSL register of the reset control module (RCM).
17.4.5.5 Very Low-Leakage Stop (VLLS3,2,1) Modes
This device contains three very low leakage modes: VLLS3, VLLS2, and VLLS1. VLLS
is often used in this document to refer to all three VLLS3, VLLS2 and VLLS1 modes.
All three of the VLLS modes can be entered from normal RUN or VLPR modes.
By executing a STOP instruction while the MCU is in a run mode and configured as per
Table 17-7
In VLLS, the on-chip voltage regulator is in its stop-regulation state while most digital
logic is powered off.
In VLLS, configure the LLWU module to enable the desired wakeup sources. The
available wakeup sources in VLLS are detailed LLWU's Chip Configuration details for
this device.
When entering VLLS, each I/O pin is latched as configured before executing VLLS.
Since all digital logic in the MCU is powered off, all port and peripheral data is lost
during VLLS. This information must be restored before ACKISO in the PMC is set.
An asserted RESET pin will cause an exit from any VLLS mode returning the device to
normal RUN mode. When exiting VLLS via the RESET pin, the PIN and WAKEUP bits
are set in the SRSL register of the reset control module (RCM).
17.4.5.6 BDM in LLS and VLLSx Modes
No debug is available while the MCU is in LLS or a VLLSx mode. LLS is a state
retention mode and all debug operation can continue after wakeup from LLS, unless
system wakeup is a reset event.
Entering a VLLSx mode causes all the BDM and debug controls and settings to be
powered off. Therefore, any breakpoints or other debug triggers set prior to entering the
VLLSx mode are lost.
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the MCU will enter the configured VLLS mode.
The LLWU interrupt must not be masked by the interrupt
controller to avoid a scenario where the system does not fully
exit stop mode on an LLS recovery.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
NOTE
Freescale Semiconductor, Inc.