mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 657

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

29.4.4.4 Power control
The ADC module remains in its idle state until a conversion is initiated. If ADACK is
selected as the conversion clock source, but the asynchronous clock output is disabled
(ADACKEN=0), the ADACK clock generator also remains in its idle state (disabled)
until a conversion is initiated. If the asynchronous clock output is enabled
(ADACKEN=1), it remains active regardless of the state of the ADC or the MCU power
mode.
Power consumption when the ADC is active can be reduced by setting ADLPC. This
results in a lower maximum value for f
29.4.4.5 Sample time and total conversion time
For short sample (ADLSMP=0), there is a 2-cycle adder for first conversion over the base
sample time of 4 ADCK cycles. For high speed conversions (ADHSC=1), there is an
additional 2-cycle adder on any conversion. The table below summarizes sample times
for the possible ADC configurations.
The total conversion time depends upon: the sample time (as determined by ADLSMP
and ADLSTS bits), the MCU bus frequency, the conversion mode (as determined by
MODE bits), the high speed configuration (ADHSC bit), and the frequency of the
conversion clock (f
Freescale Semiconductor, Inc.
ADLSMP
0
1
1
1
1
0
1
1
1
1
ADCK
ADC Configuration
ADLSTS
).
MCF51JF128 Reference Manual, Rev. 2, 03/2011
00
01
10
11
00
01
10
11
X
X
ADCK
Preliminary
ADHSC
0
0
0
0
0
1
1
1
1
1
.
Chapter 29 Analog-to-Digital Converter (ADC)
First or Single
Sample time (ADCK cycles)
6
8
24
16
10
26
18
12
6
8
Subsequent
4
6
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