mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1046

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
the I2C module is an active master, if it detects that SMBCLK low has exceeded the
value of T
byte in the transfer process. When the I2C module is a slave, if it detects the
T
START condition.
42.4.4.1.2 SCL High Timeout
When the I2C module has determined that the SMBCLK and SMBDAT signals have
been high for at least T
occur in two ways:
Any master detecting either scenario can assume the bus is free when SHTF1 rises. A
HIGH timeout occurs in scenario 2 if a master ever detects that both the BUSY bit is high
and SHTF1 is high.
When the SMBDAT signal is low and the SMBCLK signal is high for a period of time,
the other kind of timeout occurs. The time period must be defined in software. SHTF2 is
used as the flag when the time limit is reached. This flag is also an interrupt resource, so
it also triggers IICIF.
42.4.4.1.3 CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT
The following figure illustrates the definition of the timeout intervals T
T
clock cycles for a period greater than T
defined as START-to-ACK, ACK-to-ACK, or ACK-to-STOP. When CSMBCLK
TIMEOUT MEXT occurs, SMBus MEXT rises and also triggers the SLTF.
1046
1. HIGH timeout detected after a STOP condition appears on the bus
2. HIGH timeout detected after a START condition, but before a STOP condition
TIMEOUT,MIN
LOW:MEXT
appears on the bus
TIMEOUT,MIN
. When in master mode, the I2C module must not cumulatively extend its
condition, it resets its communication and is then able to receive a new
, it must generate a stop condition within or after the current data
HIGH:MAX
MCF51JF128 Reference Manual, Rev. 2, 03/2011
, it assumes that the bus is idle. A HIGH timeout can
LOW:MEXT
Preliminary
within a byte, where each byte is
Freescale Semiconductor, Inc.
LOW:SEXT
and