mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1160

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mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Reset
Memory Map and Registers
44.3.20 MCLK Divide Register (I2Sx_MDR)
Configures the MCLK Divide Ratio. Although the MCLK Divide Register can be
changed when the MCLK divided clock is enabled, additional writes to the MCLK
Divide Register are blocked while the Divider Update Flag is set. Writes to the MCLK
Divide Register when the MCLK divided clock is disabled do not set the Divider Update
Flag.
Addresses: I2S0_MDR is FFFF_8200h base + 104h offset = FFFF_8304h
1160
Bit
W
R
Reserved
Reserved
Reserved
31
0
FRACT
DIVIDE
29–26
25–24
31–20
19–12
MICS
23–0
11–0
Field
Field
30
0
29
0
28
0
0
1
This read-only bitfield is reserved and always has the value zero.
MCLK Input Clock Select
Selects the clock input to the MCLK Divider. This field cannot be changed when the MCLK divider is
enabled. See the Chip Configuration details for information about the connections to these inputs.
00
01
10
11
This read-only bitfield is reserved and always has the value zero.
This read-only bitfield is reserved and always has the value zero.
MCLK Fraction
The MCLK FRACT must be set equal or less than the MCLK DIVIDE. Sets the MCLK divide ratio such
that: MCLK output = MCLK input * ( (FRACT + 1) / (DIVIDE + 1) )
MCLK Divide
The MCLK FRACT must be set equal or less than the MCLK DIVIDE. Sets the MCLK divide ratio such
that: MCLK output = MCLK input * ( (FRACT + 1) / (DIVIDE + 1) )
27
0
SAI_MCLK pin is configured as an input that bypasses the MCLK Divider.
SAI_MCLK pin is configured as an output from the MCLK Divider and the MCLK Divider is enabled.
26
0
MCLK Divider input clock 0 selected.
MCLK Divider input clock 1 selected.
MCLK Divider input clock 2 selected.
MCLK Divider input clock 3 selected.
0
25
0
24
0
I2Sx_MCR field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
0
22
0
I2Sx_MDR field descriptions
21
0
20
0
19
0
18
0
Preliminary
17
0
FRACT
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
DIVIDE
0
6
0
5
4
0
0
3
0
2
0
1
0
0

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