mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 393

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

17.4.2.2 Stop Mode Exit Sequence
Exit from a low power stop mode is initiated by either a reset or an interrupt event. The
following sequence then executes to restore the system to a run mode (RUN or VLPR):
17.4.2.3 Aborted Stop Mode Entry
If an interrupt or a reset occurs during a stop entry sequence, the SMC can abort the
transition early and return to RUN mode without completely entering the stop mode. An
aborted entry is only possible if the reset or interrupt occurs before the PMC begins the
transition to stop mode regulation. After this point, the interrupt or reset is ignored until
the PMC has completed its transition to stop mode regulation. When an aborted stop
mode entry sequence occurs, the SMC's PMCTRL[STOPA] bit is set to 1.
17.4.2.4 Transition to Wait Modes
For wait modes (WAIT and VLPW), the CPU clock is gated off with all other clocking
continuing, as in RUN and VLPR mode operation. Some modules that support stop-in-
wait functionality have their clocks disabled in these configurations.
17.4.2.5 Transition from Stop Modes to Debug Mode
The debugger module supports a transition from STOP, WAIT, VLPS, and VLPW back
to a Halted state when the debugger has been enabled (ENBDM is 1). This transition is
initiated by executing a BDC BACKGROUND command. As part of this transition,
system clocking is re-established and is equivalent to the normal RUN and VLPR mode
clocking configuration.
Freescale Semiconductor, Inc.
1. The on-chip regulator in the PMC and internal power switches are restored.
2. Clock generators are enabled in the MCG.
3. System and bus clocks are enabled to all masters and slaves.
4. The CPU clock is enabled and the CPU begins servicing the reset or interrupt that
initiated the exit from the low power stop mode.
Aborted entry to a stop mode is not supported when an interrupt
occurs during a transition from VLPR mode to any stop mode.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Restriction
Preliminary
Chapter 17 System Mode Controller (SMC)
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