mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 257

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 11 Core
11.3.3.12 Unsupported Instruction Exception
If execution of a valid instruction is attempted but the required hardware is not present in
the processor (e.g., if the MAC is not present), an unsupported instruction exception is
generated. The instruction functionality can then be emulated in the exception handler, if
desired.
All ColdFire cores record the processor hardware configuration in the D0 register
immediately after the negation of RESET. See
Reset
Exception," for details.
11.3.3.13 Interrupt Exception
Interrupt exception processing includes interrupt recognition and the fetch of the
appropriate vector from the interrupt controller using an IACK cycle or using the
previously-supplied vector number, under control of CPUCR[IAE]. See the interrupt
chapter for details on the interrupt controller.
11.3.3.14 Fault-on-Fault Halt
The default operation of the V1 ColdFire processor is the generation of an illegal address
reset event if a fault-on-fault halt condition is detected. If CPUCR[ARD] is set, the reset
is disabled and the processor is halted as detailed below.
If a ColdFire processor encounters any type of fault during the exception processing of
another fault, the processor immediately halts execution with the catastrophic fault-on-
fault condition. A reset is required to to exit this state.
11.3.3.15 Reset Exception
Resetting the processor causes a reset exception. The reset exception has the highest
priority of any exception; it provides for system initialization and recovery from
catastrophic failure. Reset also aborts any processing in progress when the reset input is
recognized. Processing cannot be recovered.
The reset exception places the processor in the supervisor mode by setting the SR[S] bit
and disables tracing by clearing the SR[T] bit. This exception also clears the SR[M] bit
and sets the processor's SR[I] field to the highest level (level 7, 0b111). Next, the VBR is
initialized to zero (0x0000_0000). The control registers specifying the operation of any
memories (such as cache and/or RAM modules) connected directly to the processor are
disabled.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
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