mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 711

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

31.4.5 DAC Control Register 1 (DACx_C1)
Addresses: DAC0_C1 is FFFF_8500h base + 22h offset = FFFF_8522h
Freescale Semiconductor, Inc.
DACBWIEN
DACBFWM
DACBTIEN
DACBBIEN
Reserved
DMAEN
LPEN
Field
Reset
Field
Read
6–5
4–3
Write
3
2
1
0
7
Bit
DMAEN
Active high. This is a write-only bit, read it always be 0. If DAC software trigger is selected and buffer
enabled, write 1 to this bit will advance the buffer read pointer once.
0
1
DAC low power control
0
1
DAC buffer watermark interrupt enable
0
1
DAC buffer read pointer top flag interrupt enable
0
1
DAC buffer read pointer bottom flag interrupt enable
0
1
DMA enable select
0
1
This read-only bitfield is reserved and always has the value zero.
DAC buffer watermark select
7
0
The DAC soft trigger is not valid.
The DAC soft trigger is valid.
high power mode.
low power mode.
The DAC buffer watermark interrupt is disabled.
The DAC buffer watermark interrupt is enabled.
The DAC buffer read pointer top flag interrupt is disabled.
The DAC buffer read pointer top flag interrupt is enabled.
The DAC buffer read pointer bottom flag interrupt is disabled.
The DAC buffer read pointer bottom flag interrupt is enabled.
DMA disabled.
DMA enabled. When DMA enabled, DMA request will be generated by original interrupts. And
interrupts will not be presented on this module at the same time.
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
DACx_C0 field descriptions (continued)
0
DACx_C1 field descriptions
Table continues on the next page...
0
5
Preliminary
0
4
DACBFWM
Description
Description
Chapter 31 12-bit Digital-to-Analog Converter (DAC)
0
3
0
2
DACBFMD
0
1
DACBFEN
0
0
711