mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1245

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mcf51jf128

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mcf51jf128
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Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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49.4.4 IRQ Interrupts
The IRQ module can provide a source of interrupts. To cause an IRQ module interrupt
request, the following must occur:
49.4.5 Clearing an IRQ Interrupt Request
If the IRQ module interrupt pin is either falling edge and low level sensitive or rising
edge and high level sensitive, both of the following actions must occur to clear an IRQ
interrupt request:
If the IRQ module interrupt pin is falling (or rising) edge sensitive only, writing a logic 1
to the IRQACK bit in the SC register immediately clears the IRQ interrupt request even if
the enabled IRQ pin remains asserted.
Freescale Semiconductor, Inc.
• If the IRQ interrupt is falling (or rising) edge sensitive only, a falling (or rising) edge
• If the IRQ interrupt is both falling (or rising) edge and low (or high) level sensitive, a
• The IRQIE bit in the SC register must be set.
• The IRQF bit in the SC register must become set by a triggered IRQ pin. The IRQF
• The IRQ pin must have been in an inactive state for at least one clock cycle before
• Changing the IRQMOD or IRQEDG bit while the IRQPE bit is enabled may cause a
• Software provides an interrupt acknowledge by writing a logic 1 to the IRQACK bit
• And either of the following:
on the enabled IRQ pin will set the IRQF bit.
falling (or rising) edge on the enabled IRQ sets the IRQF bit. The IRQF bit remains
set as long as the IRQ pin remains asserted.
bit becomes set by the fifth clock cycle after the IRQ pin has become asserted.
becoming active.
spurious interrupt and the IRQF bit may be inadvertently cleared.
in the SC register.
• The IRQ pin returns to a deasserted logic state.
• The IRQ pin is disabled using the IRQPE bit.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 49 External Interrupt (IRQ)
1245

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