mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 915

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

38.3.4 SPI status register (SPIx_S)
This register contains read-only status bits. Writes have no meaning or effect.
When the FIFO is supported and enabled (FIFOMODE is 1): This register has four flags
that provide mechanisms to support an 8-byte FIFO mode: RNFULLF, TNEARF,
TXFULLF, and RFIFOEF. When the SPI is in 8-byte FIFO mode, the function of SPRF
and SPTEF differs slightly from their function in the normal buffered modes, mainly
regarding how these flags are cleared by the amount available in the transmit and receive
FIFOs.
Freescale Semiconductor, Inc.
SPR[3:0]
Field
3–0
When the FIFO is not supported or not enabled (FIFOMODE is
not present or is 0): Bits 3 through 0 are not implemented and
always read 0.
This 3-bit field selects one of eight divisors for the SPI baud rate prescaler. The input to this prescaler is
the bus rate clock (BUSCLK). The output of this prescaler drives the input of the SPI baud rate divider.
Refer to the description of “SPI Baud Rate Generation” for details.
000
001
010
011
100
101
110
111
SPI baud rate divisor
This 4-bit field selects one of nine divisors for the SPI baud rate divider. The input to this divider comes
from the SPI baud rate prescaler. Refer to the description of “SPI Baud Rate Generation” for details.
0000
0001
0010
0011
0100
0101
0110
0111
1000
All others Reserved
Baud rate prescaler divisor is 1
Baud rate prescaler divisor is 2
Baud rate prescaler divisor is 3
Baud rate prescaler divisor is 4
Baud rate prescaler divisor is 5
Baud rate prescaler divisor is 6
Baud rate prescaler divisor is 7
Baud rate prescaler divisor is 8
Baud rate divisor is 2
Baud rate divisor is 4
Baud rate divisor is 8
Baud rate divisor is 16
Baud rate divisor is 32
Baud rate divisor is 64
Baud rate divisor is 128
Baud rate divisor is 256
Baud rate divisor is 512
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SPI0_BR field descriptions (continued)
Preliminary
NOTE
Description
Chapter 38 Serial Peripheral Interface (SPI)
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