mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 233

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into
the operand execution pipeline. If the buffer is not empty, the IFP stores the contents of
the fetched instruction in the IB until it is required by the OEP. The instruction buffer on
the V1 core contains three longwords of storage.
For register-to-register and register-to-memory store operations, the instruction passes
through both OEP stages once. For memory-to-register and read-modify-write memory
operations, an instruction is effectively staged through the OEP twice; the first time to
calculate the effective address and initiate the operand fetch on the processor's local bus,
and the second time to complete the operand reference and perform the required function
defined by the instruction.
The resulting pipeline and local bus structure allow the V1 ColdFire core to deliver
sustained high performance across a variety of demanding embedded applications.
11.2 Memory Map/Register Description
The following sections describe the processor registers in the user and supervisor
programming models. The programming model is selected based on the processor
privilege level (user mode or supervisor mode) as defined by the S bit of the status
register (SR).
The user-programming model consists of the following registers:
Freescale Semiconductor, Inc.
• 16 general-purpose 32-bit registers (D0–D7, A0–A7)
• 32-bit program counter (PC)
• 8-bit condition code register (CCR)
• EMAC registers (refer to EMAC description)
• Decode and select/operand fetch cycle (DSOC) — Decodes instructions and
• Address generation/execute cycle (AGEX) — Calculates operand address or
• Four 48-bit accumulator registers partitioned as follows:
fetches the required components for effective address calculation, or the operand
fetch cycle
executes the instruction
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 11 Core
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