mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 350

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Registers
This register is provided so interrupt service routines can generate a forced interrupt
request without the need to perform a read-modify-write sequence on the INTC_FRC
register.
Address: INTC_SFRC is FFFF_FFC0h base + 1Eh offset = FFFF_FFDEh
15.4.9 INTC Clear Interrupt Force Register (INTC_CFRC)
The INTC_CFRC register provides a simple memory-mapped mechanism to clear a
given bit in the INTC_FRC register to negate a specific level interrupt request. The data
value on the register write causes the appropriate bit in the INTC_FRC register to be
cleared. Attempted reads of this register generate an error termination.
This register is provided so interrupt service routines can negate a forced interrupt request
without the need to perform a read-modify-write sequence on the INTC_FRC register.
Address: INTC_CFRC is FFFF_FFC0h base + 1Fh offset = FFFF_FFDFh
350
Reserved
Reset
Field
Reset
SET
Read
7–6
5–0
Read
Write
Write
Bit
Bit
This bitfield is reserved.
For data values within the 56–62 range, the corresponding bit in the INTC_FRC register is set, as defined
below.
NOTE: Data values outside this range do not affect the INTC_FRC register. It is recommended the data
111000
111001
111010
111011
111100
111101
111110
7
0
7
0
Reserved
Reserved
values be restricted to the 0x38–0x3E (56–62) range to ensure compatibility with future devices.
Bit 56, INTC_FRC[LVL7] is set
Bit 57, INTC_FRC[LVL6] is set
Bit 58, INTC_FRC[LVL5] is set
Bit 59, INTC_FRC[LVL4] is set
Bit 60, INTC_FRC[LVL3] is set
Bit 61, INTC_FRC[LVL2] is set
Bit 62, INTC_FRC[LVL1] is set
0
0
6
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
INTC_SFRC field descriptions
0
0
5
5
Preliminary
0
0
4
4
Description
0
0
3
3
SET
CLR
0
0
2
2
Freescale Semiconductor, Inc.
0
0
1
1
0
0
0
0