mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1032

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Registers
42.3.6 I2C Control Register 2 (I2Cx_C2)
Addresses: I2C0_C2 is FFFF_81C0h base + 5h offset = FFFF_81C5h
1032
GCAEN
ADEXT
HDRS
Field
Reset
Field
Read
Write
7
6
5
Bit
I2C1_C2 is FFFF_81D0h base + 5h offset = FFFF_81D5h
I2C2_C2 is FFFF_81E0h base + 5h offset = FFFF_81E5h
I2C3_C2 is FFFF_81F0h base + 5h offset = FFFF_81F5h
GCAEN
The C1[TX] bit must correctly reflect the desired direction of transfer in master and slave modes for the
transmission to begin. For example, if the I2C module is configured for master transmit but a master
receive is desired, reading the Data register does not initiate the receive.
Reading the Data register returns the last byte received while the I2C module is configured in master
receive or slave receive mode. The Data register does not reflect every byte that is transmitted on the I2C
bus, and neither can software verify that a byte has been written to the Data register correctly by reading
it back.
In master transmit mode, the first byte of data written to the Data register following assertion of MST (start
bit) or assertion of RSTA (repeated start bit) is used for the address transfer and must consist of the
calling address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
General call address enable
Enables general call address.
0
1
Address extension
Controls the number of bits used for the slave address.
0
1
High drive select
Controls the drive capability of the I2C pads.
0
1
7
0
Disabled
Enabled
7-bit address scheme
10-bit address scheme
Normal drive mode
High drive mode
ADEXT
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
I2Cx_D field descriptions (continued)
I2Cx_C2 field descriptions
Table continues on the next page...
HDRS
0
5
Preliminary
SBRC
0
4
Description
Description
RMEN
0
3
0
2
Freescale Semiconductor, Inc.
AD[10:8]
0
1
0
0